GLES offscreen rendering
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Updated
Jan 28, 2024 - C
GLES offscreen rendering
secure software and hardware-accelerated AES library
Experimental implementation of FRED for Linux.
Implementation (VHDL) and verification of the accelerator proposed in the paper "Hardware Accelerator for Shapelet Distance Computation in Time-Series Classification", from May 2020
Hardware/Software Framework for the Development of Linux Block I/O Accelerators
CSS and Markup hardware-accelerated library in C
2D N-body, hardware accelerated gravity simulator with custom and interactive maps
This framework was part of the Diploma thesis titled "Architectures and Implementations of the Neural Network LeNet-5 in FPGAs". The main goal of this thesis was to create a LeNet-5 implementation in an FPGA development board, but also form a reusable framework/workflow which can be modified to model and develop other Neural Networks as well.
Hardware Software Co-Design Course Project
ffmpeg 4.0.3 for rtd1296 kernel 4.9
UltraZed Development
32-bit CRC Hardware Accelerator and Custom Instructions implemented (in Verilog) in Altera's FPGA board.
HLS SHA-3 Accelerator
This repo has codes for hardware accelerator design for CNNs using high level synthesis from Altera.
Matrix Multiplication in Hardware
The Hailo PCIe driver is required for interacting with a Hailo device over the PCIe interface
Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs
Motion recognition with artificial intelligence on STM32
doppioDB - A hardware accelerated database
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