The Task Parallel System Composer (TaPaSCo)
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Updated
Jun 6, 2024 - Verilog
The Task Parallel System Composer (TaPaSCo)
Hardware acceleration of image scaling
Real-Time Hardware Sorter, Using A Multi-Dimensional Sorting Algorithm
The IPPro is a 16-bit signed fixed-point, five-stage balanced pipelined RISC architecture that exploits the DSP48E1 features and provides balance among performance, latency and efficient resource utilization.
XCrypto: a cryptographic ISE for RISC-V
Specialized FPU for Fast Inverse Square Root Algorithm
This project is being developed as part of a Master's degree research sponsored by Brazil's CNPQ. It's goal is to design a hardware architecture to accelerate the AV1 arithmetic encoder.
Hardware accelerator for convolutional neural networks
FlexDriver IoT authentication offload example AFU.
grayscale conversion system and simple convolution system
sequence detector with overlapped 2 patterns 010111 or 1101
Computer Organisation Project for EE2003
[ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
Application of the RANSAC algorithm in embedded C and Verilog for Altera Nios II and Cyclone IV E.
Verilog implementation of an ordinary differential equation (ODE) solver accelerator chip ― **INCOMPLETE IMPLEMENTATION**
Gravitational simulation of the N-body problem using FPGA hardware acceleration
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