Laboratories of 'Microelectronic Systems' course at PoliTo
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Updated
Jun 7, 2021 - VHDL
Laboratories of 'Microelectronic Systems' course at PoliTo
A digital design implementation of a FIFO memory circuit using VHDL simulated in Quartus.
An attempt of creating faster multiplication circuit with HDL VHDL
🏄 Custom IP for vector operations
A repo to host research contributions for summer 2017
A VHDL implementation of a RISC-V model processor
MC2101 is an open-source single-core microcontroller system based on a 32-bit RV32IM RISC-V core
This repository consists of basic VHDL codes intended for a brief revision.
Five stages pipeline-processor CMP Core i(-1)
Introduction to hardware synthesis and hardware design.
Hardware component that performs a convolutional encode
Some digital circuits designed in ISE for FPGA using VHDL.
Design & Verification of IP Cores and ICs, Artificial Intelligence
VHDL implementation of the WiSARD Neural Network (Wilkie, Stoneham and Aleksander Recognition Device)
A project to build a MIPS processor
Few of my VHDL hardware design for Xilinx Spartan 6 board
HLSM with memory design for max pooling algorithm.
Progetto universitario. Realizzazione in VHDL, test e sintesi con Xilinx Vivado per FPGA di un CIC filter.
Prova finale di Reti Logiche a.a. 2022/2023 del Politecnico di Milano
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