mips-architecture
Here are 61 public repositories matching this topic...
A nearly holistic CPU with MIPS architecture implementing 50+ instructions together with cache and TLB.
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Jan 3, 2018 - Verilog
Computer Organization and Design (2nd year - 3rd semester)
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Jan 5, 2018 - Verilog
Verilog Description for a 32bit MIPS Processor
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Feb 10, 2018 - Verilog
Pipelined MIPS architecture created in Verilog. Includes data forwarding and hazard detection.
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Apr 1, 2018 - Verilog
Single-Cycle and 5-stage Pipelined SoC
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May 26, 2018 - Verilog
A verilog-based MIPS processor with pipelining
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Jun 28, 2018 - Verilog
University of Tehran Computer Architecture Lab F96 - mirror of https://gitlab.com/hadi_sfr/UT_CA_Lab
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Jun 30, 2018 - Verilog
Collecting some verilog modules from past and future.
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Nov 7, 2018 - Verilog
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May 29, 2019 - Verilog
A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
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Sep 3, 2019 - Verilog
A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall
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Oct 26, 2019 - Verilog
32-bit ALU design for MIPS.
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Nov 21, 2019 - Verilog
Tiny series: A handwritten CPU of MIPS instruction set.
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Mar 27, 2020 - Verilog
5-stage pipelined 32-bit MIPS microprocessor in Verilog
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Apr 3, 2020 - Verilog
5 stage pipelined MIPS-32 processor
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Apr 20, 2020 - Verilog
Pipline MIPS processor implementation on Basys 3 with hazard handling and memory mapped IO.
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May 16, 2020 - Verilog
A simple MIPS processor implemented using Verilog capable of supporting basic I,J and R type instructions. Built using Xilinx Vivado 2019.1
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May 20, 2020 - Verilog
32-bit MIPS CPU implementation on Verilog
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May 26, 2020 - Verilog
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