VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
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Jan 4, 2022 - Verilog
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mixed-signal
Here are 6 public repositories matching this topic...
Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license
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Jul 30, 2024 - Verilog
Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process, embedded in efabless Caravel
audio
magic
asic
wavelet
audio-processing
mixed-signal
netgen
integrated-circuits
cochlea
skywater
130nm
switched-capacitor
caravel-shuttle
xshem
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Sep 24, 2022 - Verilog
A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier
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May 31, 2022 - Verilog
3bit digitally controlled PWM Generator using eSim, using ngveri(Makerchip) and ngspice
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Jun 18, 2022 - Verilog
Verilog-A test block for estimating noise and offset of a dynamic comparator in a transient simulation. Uses the Confidence-Boosting concept published at NEWCAS 2024.
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Nov 10, 2024 - Verilog
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