modelsim
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Computer Architecture Lab - Assignments - Fall 2023
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Feb 1, 2024 - SystemVerilog
A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL
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Jun 5, 2023 - SystemVerilog
This project was a nice idea I had to build a digital logic clock on the DE1-SOC FPGA, while practicing System-verilog, Asynchronous design, and advanced debugging techniques
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Sep 28, 2022 - SystemVerilog
UART Receiver and Transmitter using Terasic DE-10 Standard FPGA
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Aug 4, 2022 - SystemVerilog
Simple Central Processing Unit (CPU) Design using Terasic DE-10 Standard FPGA
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Aug 3, 2022 - SystemVerilog
Basic Stopwatch Design using Terasic DE-10 Standard FPGA
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Jul 30, 2022 - SystemVerilog
DS1302 Real-time Clock (RTC) Module Interfacing with Terasic DE-10 Standard FPGA
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Jul 30, 2022 - SystemVerilog
Scrolling Display Implemented With Digital Design Concepts on De1-SoC
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Mar 12, 2022 - SystemVerilog
Repository of homeworks and projects of the verification class from Bootcamp Pre-Silicon at ITESO with INTEL
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Jan 10, 2022 - SystemVerilog
CAPIPrecis a Coherent Accelerator Processor Interface (CAPI) Abstract Layer
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Oct 22, 2021 - SystemVerilog
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Jan 9, 2021 - SystemVerilog
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
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Nov 25, 2019 - SystemVerilog
FPGA stuff
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Sep 10, 2019 - SystemVerilog
Pipeline Processor based on RISC-V, implemented forwarding and hazard detection units
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Apr 23, 2019 - SystemVerilog
Single-Cycle RISC-V Processor in systemverylog
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Apr 23, 2019 - SystemVerilog
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