SystemRDL 2.0 language compiler front-end
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Updated
May 9, 2024 - Python
SystemRDL 2.0 language compiler front-end
Control and status register code generator toolchain
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Generate UVM register model from compiled SystemRDL input
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
Parse register dumps with minimal overhead
A GUI simulator/interpreter for custom assembly language, written in python/tkinter
Smeagle Python - generate facts from ELF with debug
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