RISC-V
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
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Методические материалы по разработке процессора архитектуры RISC-V
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Jun 1, 2024 - SystemVerilog
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
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May 31, 2024 - SystemVerilog
VeeR EL2 Core
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May 31, 2024 - SystemVerilog
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
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Jun 1, 2024 - SystemVerilog
Creating a risc-v processor
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Apr 4, 2024 - SystemVerilog
Syntacore scr1 iALU verification example
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Mar 7, 2024 - SystemVerilog
DUTH RISC-V Superscalar Microprocessor
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Apr 25, 2024 - SystemVerilog
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
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Jan 18, 2024 - SystemVerilog
A Pipelined Implementation of the RV32I Processor
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Jan 12, 2024 - SystemVerilog
Implementation of 3 stage pipelined processor based on RISC-V Instruction Set Architecture
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Dec 30, 2023 - SystemVerilog
RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
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Sep 21, 2023 - SystemVerilog
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
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Sep 18, 2023 - SystemVerilog
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Sep 15, 2023 - SystemVerilog