Supports 12 MIPS instructions
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Updated
May 6, 2022 - C++
Supports 12 MIPS instructions
Spring 2021 UCM CSE140 (Single-cycle MIPS CPU) & (Pipelined MIPS CPU)
Verilog descriptions of MIPS single-cycle, multi-cycle & booth multiplier.
simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL.
design a single-cycle MIPS CPU in C++. Single-cycle CPU program needs to be able to execute the following 10 instructions LW, SW, ADD, SUB, AND, OR, SLT, NOR, BEQ, J.
This project was designed to run on Nexys A7 Artix-7 FPGA Trainer Board. This processor written in System Verilog can run I-Type, R-Type, B-Type, S-Type RISC-V commands. The current instruction set that has been uploaded here finds the greatest common divisor of two numbers.
👷♀️Computer Architecture Course Projects, University of Tehran
This repository holds files related to the development of a Single-Cycle Processor developed during the Digital Systems Architecture course.
A single cycle pipeline processor based on MIPS instruction set architecture (ISA)
MIPS processor designed in Verilog.
A digital design project for a MIPS Reduced Instruction Set Computer (RISC) single-cycle processor design that supports 32-bit MIPS instructions with an 8-bit wide datapath, on a 256x32 ROM and 256x8 RAM, implemented through structural VHDL
Few Verilog Programs I had wrote for EC-220 Computer System Architecture
Single Cycle MIPS Processor implementation, Computer Assignment for Computer Architecture course in Ferdowsi University of Mashhad
Implementación del procesador monociclo RISC-V en System Verilog.
Single Cycle CPU design (RISC architecture) developed in Xilinx ISE 14.7 using Verilog
Processor Design of RV32I 5-Stage Pipelined CPU
A Verilog implementation of a single cycle processor using the LEGv8 instruction set architecture
This is a simple implementation of the MIPS single cycle processor that is described and taught in the book of "Computer Organisation and Design" from Patterson and Hennessy.
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