behavioral simulation of a subset of SPARC-like instructions // CPSC 3300 (Computer Systems Organization) Fall 2020 - PROGRAM 2
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Jul 16, 2021 - C
behavioral simulation of a subset of SPARC-like instructions // CPSC 3300 (Computer Systems Organization) Fall 2020 - PROGRAM 2
behavioral simulation of a subset of SPARC-like instructions // CPSC 3300 (Computer Systems Organization) Fall 2020 - PROGRAM 3
Modified QEMU which generates full instruction & data address traces. Configure with --enable-full-trace. Env vars: QEMU_SKIP_FIRST_INST skips tracing of the first N instructions, QEMU_TRACE_LIMIT limits the amount of instructions traced, and QEMU_TRACE_OUTPUT configures the output file (stderr by default). Working on SPARC, SPARC64, PPC, PPC64.…
behavioral simulation of a subset of SPARC-like instructions // CPSC 3300 (Computer Systems Organization) Fall 2020 - PROGRAM 1
Minimalist cooperative operating system supporting multiple tasks with MMU protection
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.
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