A hardware-verified 8-bit Synchronous FIFO implemented on Xilinx Spartan-6 FPGA using Verilog HDL. Features robust signal debouncing, power-on reset logic, and real-time status monitoring.
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Updated
Apr 15, 2026 - SystemVerilog
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synchronous-fifo
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Synchronous FIFO implementation in Verilog with testbench and simulation waveforms
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Updated
May 21, 2026 - Verilog
A hardware-verified 8-bit Synchronous FIFO implemented on Xilinx Spartan-6 FPGA using Verilog HDL. Features robust signal debouncing, power-on reset logic, and real-time status monitoring.
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Updated
May 16, 2026 - SystemVerilog
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