Control and Status Register map generator for HDL projects
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Updated
Jul 25, 2024 - Python
Control and Status Register map generator for HDL projects
Spice to Verilog Converter
Example of Python and PyTest powered workflow for a HDL simulation
Templates generator: make Verilog/SystemVerilog module template by parameters and ports list
Segundo proyecto para el curso de Arquitectura de Computadores. La idea es hacer un ASIP (Application Specific Set Processor) que genere interpolación de imagen por medio de un compilador, código en ensamblador, un procesador pipeline y scripts en alto nivel.
An approachable testing framework for digital hardware
This repository aims to automatically generates source files for HDL
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