AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.
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Mar 22, 2017 - SystemVerilog
AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.
Simple ipod made using System Verilog and implemented on the De1Soc
Quartus II project for a basic interface for writing in a LCD screen using a PS2 keyboard using Altera DE2-70 board
Pulse Width Modulator programmed through an Advanced Peripheral Bus interface
16 bit serial multiplier in SystemVerilog
A prototype of Concolic Testing engine for SystemVerilog, developed as part of PFN summer internship 2018.
Synthesizable System Verilog implementation of bottom-up merge sort
Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verification of verilog systems.
Rešenja zadataka sa vežbi iz predmeta "Projektovanje namenskih računarskih struktura 2"
This repository aims to automatically generates source files for HDL
My solutions for Bilkent University CS224 Computer Organization Labs (Spring 2019). Includes assembly programming assignments together with various processor designs in System Verilog HDL
RISC-V five stage pipline CPU
Multiple DUT with parallel stimulus
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