systemverilog
Here are 14 public repositories matching this topic...
My technical blog: ramblings of a digital chip designer on Python, SystemVerilog and all that jazz...
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Apr 12, 2021 - HTML
Created a RISC-V Pipelined processor in SystemVerilog with features like Caches, Prefetching, History Table. Skills employed: SystemVerilog, Verdi, Logic Design, Computer Architecture
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Jul 2, 2023 - HTML
Verilog for a Field Programmable Gate Array Engineer with Xilinx Vivado Design Suite.
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Oct 14, 2020 - HTML
Bilkent University CS223 Lab Project
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Oct 23, 2019 - HTML
Vivado project implemented on SystemVerilog for Basys 3
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Apr 30, 2018 - HTML
A Dual Core MIPS CPU. Feature 11 32-bit instructions, 8-bit datapath, Arbiter, MMU, and ROM. Verified using RAM module which encoded a Fibonacci program and via Randomized test bench.
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Mar 6, 2023 - HTML
Complete Implementation of a Integer Neural Network using SystemVerilog targeted to the Pynq-Z1 board.
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Jan 30, 2022 - HTML
uvm examples and source code
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Jun 12, 2022 - HTML
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Jun 19, 2019 - HTML
SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol
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Jul 1, 2022 - HTML
RISC-V Ibex core with Wishbone B4 interface
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Dec 24, 2019 - HTML
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