RISC-V Ibex core with Wishbone B4 interface
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Updated
Dec 24, 2019 - HTML
RISC-V Ibex core with Wishbone B4 interface
SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol
uvm examples and source code
Complete Implementation of a Integer Neural Network using SystemVerilog targeted to the Pynq-Z1 board.
A Dual Core MIPS CPU. Feature 11 32-bit instructions, 8-bit datapath, Arbiter, MMU, and ROM. Verified using RAM module which encoded a Fibonacci program and via Randomized test bench.
My technical blog: ramblings of a digital chip designer on Python, SystemVerilog and all that jazz...
Created a RISC-V Pipelined processor in SystemVerilog with features like Caches, Prefetching, History Table. Skills employed: SystemVerilog, Verdi, Logic Design, Computer Architecture
Verilog for a Field Programmable Gate Array Engineer with Xilinx Vivado Design Suite.
Bilkent University CS223 Lab Project
Vivado project implemented on SystemVerilog for Basys 3
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