Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
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Updated
Oct 20, 2023 - Verilog
Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.
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The project description of this project was the major project in the Computer Architecture course. It's a RISC-V processor and tested on Nexys A7 kit.
"Repository containing a collection of Verilog code modules and test bench for digital design projects. "
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