Contains solutions of Architecture lab CS321/CS322 (IIT Patna) assignments using Verilog,etc.
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Updated
Mar 21, 2019 - Assembly
Contains solutions of Architecture lab CS321/CS322 (IIT Patna) assignments using Verilog,etc.
CS 552 term project : functional design of a microprocessor called the WISC-SP13
A simple five-stage pipeline MIPS CPU in Verilog.
8085,8086,AVR
Nand2Tetris for MiSTer (as a learning experience for me).
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