verilog-hdl

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Here are 7 public repositories matching this topic...

MalakSadek / StaticTimingAnalyzer

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A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)

python c html json graph-algorithms scl verilog logic-gates verilog-hdl logic-circuit static-timing-analysis

Updated Mar 25, 2021
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peltierchip / Dragon

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Snake game using Verilog on Spartan®-6 FPGA

game xilinx verilog-hdl fpga-programming

Updated Jun 29, 2018
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ihdavjar / EEL2020_Project_EVM

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This repo contains the EEL2020 course project, which was instructed to be made in hindi.

video-editing verilog-hdl adobe-photoshop digital-logic-design electronic-voting-system

Updated Jul 2, 2024
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ahmedishraq / CSE460-Lab

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CSE460 - VLSI Design

vhdl coq verilog-hdl verilog-project vlsi-design bracucse460

Updated Feb 9, 2023
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vinayaktrivedi / CS220-labs

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Verilog CS220 synthesised codes

verilog-hdl

Updated Mar 21, 2018
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nickschiffer / cla_adder_7seg

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4bit_CLA_Adder_7seg in Xilinx Vivado Verilog

verilog-hdl xilinx-fpga nexys4ddr

Updated Mar 6, 2018
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AbigailParrales / DigitalSystemsLab

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verilog-hdl

Updated Aug 8, 2017
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verilog-hdl

Here are 7 public repositories matching this topic...

MalakSadek / StaticTimingAnalyzer

peltierchip / Dragon

ihdavjar / EEL2020_Project_EVM

ahmedishraq / CSE460-Lab

vinayaktrivedi / CS220-labs

nickschiffer / cla_adder_7seg

AbigailParrales / DigitalSystemsLab

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