Trying to learn Wishbone by implementing few master/slave devices
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Updated
Jan 7, 2019 - SystemVerilog
Trying to learn Wishbone by implementing few master/slave devices
A Verilog I2C initializer with integrated RS232 debugger. *** New v1.1 Supports I2C CLK stretch and separate IO buffers for driving Efinix's IO primitive.
An attempt at making a customised RISC processor with five pipelined stages and supporting all RISC-V instruction set
This testbench is based on SV and UVM Class based to verify Verilog HDL Design
Verilog Codes of various Inter Device Communication Protocols
RTL design and implementation of a 4x4 Network-on-Chip (NoC) with a mesh topology. This project includes SystemVerilog modules for buffer units, routing units, switch allocators, switches, routers, and nodes, along with comprehensive high-level testing scenarios. Developed as part of a Core-Based Embedded System Design course.
Mips Multi-Cycle, Computer Architecture course, University of Tehran
VerilogHDL implementation of One-Time Password Algorithm (HOTP)
Verilog Codes for various Design
KL10PV (also called "model B") CPU implemented in SystemVerilog for Xilinx FPGA from MP00301_KL10PV_Jun80 PDFs trying to remain faithful to the original while I learn Verilog
ROCC accelerator ISA based neuroSynapse
BDD Gherkin implementation in native SystemVerilog, based on UVM.
Verification of D-FF using UVM on EDA playground
This repository contains all the Verilog codes and their testbenches that I have compiled as a part of my academic journey in Electronics and Communication Engineering.
Creating a risc-v processor
Basics of Verilog implementation
Mips Single-Cycle, Computer Architecture course, University of Tehran
Verilog-HDL implementation of a simple 4-bit PC.
A Tic-Tac-Toe with multiple level levels and flashing lights implementation using Hardware Definition Language (Verilog) and DE10-Lite Altera Max 10 FPGA.
An Implementation of MIPS processor with single/multi-cycle architecture using SystemVerilog language.
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