verilog-hdl
Here are 349 public repositories matching this topic...
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 7…
-
Updated
Nov 13, 2024 - Verilog
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
-
Updated
Apr 30, 2024 - Verilog
High throughput JPEG decoder in Verilog for FPGA
-
Updated
Mar 5, 2022 - Verilog
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
-
Updated
Jun 20, 2024 - Verilog
5-stage pipelined 32-bit MIPS microprocessor in Verilog
-
Updated
Apr 3, 2020 - Verilog
A simple implementation of a UART modem in Verilog.
-
Updated
Nov 10, 2021 - Verilog
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F…
-
Updated
Jan 29, 2024 - Verilog
2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)
-
Updated
May 26, 2019 - Verilog
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
-
Updated
Jan 17, 2018 - Verilog
中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU
-
Updated
Mar 21, 2021 - Verilog
Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
-
Updated
Jul 31, 2022 - Verilog
Gigabit Ethernet UDP communication driver
-
Updated
Jul 26, 2019 - Verilog
Implementing Different Adder Structures in Verilog
-
Updated
Sep 3, 2019 - Verilog
FPGA implementation of deflate (de)compress RFC 1950/1951
-
Updated
May 2, 2019 - Verilog
Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
-
Updated
Nov 25, 2020 - Verilog
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
-
Updated
Jul 9, 2023 - Verilog
This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.
-
Updated
Nov 30, 2022 - Verilog
Interface Protocol in Verilog
-
Updated
Aug 2, 2019 - Verilog
Improve this page
Add a description, image, and links to the verilog-hdl topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the verilog-hdl topic, visit your repo's landing page and select "manage topics."