A Tic-Tac-Toe with multiple level levels and flashing lights implementation using Hardware Definition Language (Verilog) and DE10-Lite Altera Max 10 FPGA.
-
Updated
Mar 9, 2018 - SystemVerilog
A Tic-Tac-Toe with multiple level levels and flashing lights implementation using Hardware Definition Language (Verilog) and DE10-Lite Altera Max 10 FPGA.
An Implementation of MIPS processor with single/multi-cycle architecture using SystemVerilog language.
My Coding Portfolio
MIPS Single cycle Verilog Implementation
MIPS multi cycle Verilog Implementation
Interfaces of computing systems
ARM Multi Cycle Processor Core HDL Description
IceCream for SystemVerilog: Never use $display and `uvm_info to debug SystemVerilog again.
SystemVerilog , Verilog , Verilog-A , Verilog-AMS tutorial
This repository contains all the Verilog codes and their testbenches that I have compiled as a part of my academic journey in Electronics and Communication Engineering.
Creating a risc-v processor
Basics of Verilog implementation
Mips Single-Cycle, Computer Architecture course, University of Tehran
Verilog-HDL implementation of a simple 4-bit PC.
RTL design and implementation of a 4x4 Network-on-Chip (NoC) with a mesh topology. This project includes SystemVerilog modules for buffer units, routing units, switch allocators, switches, routers, and nodes, along with comprehensive high-level testing scenarios. Developed as part of a Core-Based Embedded System Design course.
Mips Multi-Cycle, Computer Architecture course, University of Tehran
This testbench is based on SV and UVM Class based to verify Verilog HDL Design
VerilogHDL implementation of One-Time Password Algorithm (HOTP)
Add a description, image, and links to the verilog-hdl topic page so that developers can more easily learn about it.
To associate your repository with the verilog-hdl topic, visit your repo's landing page and select "manage topics."