verilog-hdl
Here are 22 public repositories matching this topic...
Crane Game using Custom Pipelined Processor
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Sep 17, 2022 - VHDL
The purpose is to investigate latches, flip-flops, and registers. DA CS 603
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Nov 12, 2018 - VHDL
Implementation of a sampler using the XADC mounted on the Arty A7-35T development board and the PmodAD1 by Digilent (AD7476A).
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Apr 2, 2022 - VHDL
This repository is intended for students who study Electrical Engineering at University of Baghdad, as well as anyone else who wants to learn about FPGA programming.
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May 23, 2023 - VHDL
Creates a simple major arpeggiator using a Vivado IP core on a Nexys A7 FPGA board.
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May 16, 2020 - VHDL
this repo contains 2 assignments during my computer organization and architecture course.
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Feb 13, 2024 - VHDL
The implementation of a Five-Stage Pipelining RISC-V Microprocessor in Verilog HDL
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Nov 14, 2022 - VHDL
Verilog sources for FPGA Zybo board implementing vision algorithms.
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Jul 1, 2018 - VHDL
Proyecto desarrollado para la asignatura de Laboratorio de Electrónica Digital
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Feb 15, 2019 - VHDL
To receive the clock and data from clock and data interfaces, apply the DSP algorithm on the transmitted data. The DSP algorithm includes differential encoding, scrambling and convolutional encoding, generate test data pattern to be used in the self-test mode of operation
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Feb 10, 2019 - VHDL
Implementation of a Canny-Edge Detector on a Zybo-Z7 FPGA.
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Mar 12, 2022 - VHDL
Some examples of Veitch-Karnaugh maps solved using verilog language developed as coursework of Architecture and Computer Organization I- @puc Minas
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Jan 31, 2018 - VHDL
Kuantek University Program
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Oct 12, 2023 - VHDL
FPGA Implementation of Full Search Block matching using an asynchronous handshake based FSM.
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Nov 2, 2020 - VHDL
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