verilog-hdl
Here are 513 public repositories matching this topic...
A project by Verilog HDL to play the whac-a-mole game on BASYS 2 FPGA board.
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Sep 25, 2019 - Verilog
A real time clock module is designed and simulated in ModelSim. The language used is Verilog HDL.
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Jul 27, 2020 - Verilog
A pipelined implementation of MIPS32 processor using Verilog HDL
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May 18, 2021 - Verilog
Crane Game using Custom Pipelined Processor
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Sep 17, 2022 - VHDL
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Sep 11, 2023 - C
Open Source Verilog Modules
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Jan 25, 2023 - Verilog
This is a university project. It is an implementation ant testing of MIPS processor in verilog. It is not synthesizable yet
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Jun 12, 2023 - C
This repository focuses on how to design a PWM Generator with variable Duty cycle
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Nov 22, 2023 - Verilog
Some exercises on verilog.
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Dec 21, 2023 - Verilog
All basic to advanced hardware models which are used in VLSI Frontend Design using Verilog HDL
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Jan 16, 2024 - Verilog
An 4-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.
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May 16, 2021 - Verilog
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Aug 20, 2022
Contains vim dotfiles configured for verilog, C++ & some stuff for VLSI
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Aug 14, 2021 - Vim Script
This repo contains the EEL2020 course project, which was instructed to be made in hindi.
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Jul 2, 2024 - HTML
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May 7, 2017 - Verilog
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