This repository is for Computer Organization course. The work in this repository aims to show skills in scripting circuits using Verilog and programming FPGA board.

A SystemVerilog style guide.

🖼✏️ My first baby steps into the world of image processing

A python program to generate a Pseudo Random Noise sequence called WSLCE

This project consists of a verilog code for calculating the day of a week from any given date between the years 1700 to 2300

This repository contains all the lab assignments done during the course ECE270-Embedded Logic Design using Verilog HDL.

A pipelined implementation of MIPS32 processor using Verilog HDL MIPS32 is a Reduced Instruction Set Computer (RISC) architecture, and here, this particular processor is designed in Verilog HDL with 5 phases of pipeline, namely Instruction Fetch (IF), Instruction Decode (ID), Execution (EX), Memory (MEM), Write Back (WB). This design has a small…

A Verilog I2C initializer with integrated RS232 debugger. *** New v1.1 Supports I2C CLK stretch and separate IO buffers for driving Efinix's IO primitive.

Implementation of IF, ID, EX, MEM, WB and two stages units used in hazard detection and the forwarding unit, thus realizing a complete RISC-V processor prototype.

This Repository contains my code for the Digital System Design (DSD) lab during my 3rd Semester of B.Tech.

Simplest project of a soft-cpu (picorv32) with a complete software environment.

Risc-V 32i processor written in the Verilog HDL

Processador RISC-V multi ciclo com implementação RV32I construído em alguns dias de folga.

Solutions to the practice questions of Verilog given on HDLBits

Summer School on Full Stack Open-Source Ecosystem for Processor Based Chip Design

Using Verilog HDL

Verilog Project