FPGA Cryptography for High-Level Synthesis
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Updated
Aug 3, 2021 - C++
FPGA Cryptography for High-Level Synthesis
High Level synthesis of data transfer in Vivado, Vivado HLS
Extract the propagation delay of the signal (inside the microcircuit housing) from the .csv file with delays from Vivado. The output file is generated in the format necessary for import into CES (mentor graphics).
What's that weird looking CPU?
High level synthesis projects and practices
MNIST accelerator using pynq-z2 and the binary qunatization
Hardware accelerated Julia set explorer running on Ultra96
Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)
Gate-Level Simulation on a GPU
Source codes for High Level Synthesis for Fixed Progammable Gate Arrays (FPGAs). Can be converted to RTL using Vivado HLS or SDSoC.
FPGA Accelerator for CNN using Vivado HLS
Machine learning on FPGAs using HLS
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