vivado
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Extract the propagation delay of the signal (inside the microcircuit housing) from the .csv file with delays from Vivado. The output file is generated in the format necessary for import into CES (mentor graphics).
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Feb 2, 2020 - C++
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Jan 20, 2022 - C++
What's that weird looking CPU?
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May 26, 2021 - C++
High level synthesis projects and practices
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Apr 13, 2021 - C++
High Level synthesis of data transfer in Vivado, Vivado HLS
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May 16, 2022 - C++
Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)
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Oct 13, 2020 - C++
MNIST accelerator using pynq-z2 and the binary qunatization
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Oct 22, 2022 - C++
Gate-Level Simulation on a GPU
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Nov 22, 2016 - C++
FPGA Cryptography for High-Level Synthesis
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Aug 3, 2021 - C++
Source codes for High Level Synthesis for Fixed Progammable Gate Arrays (FPGAs). Can be converted to RTL using Vivado HLS or SDSoC.
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Apr 5, 2019 - C++
Hardware accelerated Julia set explorer running on Ultra96
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May 7, 2022 - C++
FPGA Accelerator for CNN using Vivado HLS
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Oct 25, 2021 - C++
Machine learning on FPGAs using HLS
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Jun 11, 2024 - C++
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