Machine learning on FPGAs using HLS
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Updated
Jun 13, 2024 - C++
Machine learning on FPGAs using HLS
MNIST accelerator using pynq-z2 and the binary qunatization
High Level synthesis of data transfer in Vivado, Vivado HLS
Hardware accelerated Julia set explorer running on Ultra96
FPGA Accelerator for CNN using Vivado HLS
FPGA Cryptography for High-Level Synthesis
What's that weird looking CPU?
High level synthesis projects and practices
Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)
Extract the propagation delay of the signal (inside the microcircuit housing) from the .csv file with delays from Vivado. The output file is generated in the format necessary for import into CES (mentor graphics).
Source codes for High Level Synthesis for Fixed Progammable Gate Arrays (FPGAs). Can be converted to RTL using Vivado HLS or SDSoC.
Gate-Level Simulation on a GPU
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