vivado
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ALEF_Vivado (Automated Library Evaluation Framework) is a tool coded up in Python that automates the synthesis and implementation flow of Xilinx Vivado Tool by running Tcl Scripts for the input Verilog/SystemVerilog modules and finally generating a CSV file containing several components of the generated power, timing, and utilization reports.
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Mar 11, 2023 - Verilog
FPGA Audio Effect System project for Electronic Engineering course. This project spanned two semesters and was my final year project
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Oct 11, 2020 - Verilog
I am trying to develop my skills through daily practice and consistency.
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Jun 8, 2024 - Verilog
Display of various animated digital and analog clock using VGA control in FPGA
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May 23, 2018 - Verilog
Useful scripts to run and configure InTime with the Xilinx Vivado tools.
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Sep 6, 2021 - Verilog
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Jul 19, 2022 - Verilog
A Sound and Sight Entertainment System (SSES) implemented on Basys3 FPGA Board
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May 13, 2021 - Verilog
Global Dark Mode for ALL apps on ANY platforms.
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Oct 3, 2023 - Verilog
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
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May 21, 2024 - Verilog
HITSZ 2024 数字电路技术实验 FPGA Verilog 代码仓库
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May 30, 2024 - Verilog
Implementation of a circuit that generates a video signal for a specific display format.
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Jun 13, 2018 - Verilog
Sobel Filter Verilog implementation
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May 20, 2024 - Verilog
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