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xilinx

Here are 43 public repositories matching this topic...

trabucayre / openFPGALoader

Universal utility for programming FPGA

fpga intel cyclone xilinx lattice bitstream arty gowin trenz-gowin-littlebee

Updated Nov 13, 2024
C++

Xilinx / SDAccel_Examples

SDAccel Examples

c aws fpga cpp opencl xilinx sdx sdaccel nimbix

Updated May 20, 2022
C++

Xilinx / CHaiDNN

HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

deep-neural-networks inference dnn xilinx alexnet googlenet embedded-vision xilinx-ultrascale-mpsocs

Updated Jul 9, 2019
C++

definelicht / hlslib

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

cmake fpga hpc xilinx sdaccel high-level-synthesis vivado-hls intel-fpga vitis intel-fpga-opencl

Updated Apr 23, 2024
C++

fpgasystems / Vitis_with_100Gbps_TCP-IP

100 Gbps TCP/IP stack for Vitis shells

tcp xilinx vitis network-kernel

Updated Apr 23, 2024
C++

Xtra-Computing / ThunderGP

HLS-based Graph Processing Framework on FPGAs

hls graph-processing xilinx fpgas accelerators programmability graph-analytic-algorithm

Updated Oct 11, 2022
C++

UCLA-VAST / AutoBridge

[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.

frequency fpga xilinx floorplan vivado-hls hls-compilation hls-designs

Updated Jan 3, 2023
C++

cea-wind / SimpleTPU

A FPGA Based CNN accelerator, following Google's TPU V1.

fpga hls accelerator cnn xilinx synthesis tpu cnn-accelerator

Updated Jul 25, 2019
C++

mithro / ixo-usb-jtag

usb-jtag - Altera USB Blaster Emulation with a FX2

fpga xilinx altera usb-devices openocd jtag numato-opsis digilent-atlys cypress-fx2 ezusb digilent opsis numato urjtag

Updated Jul 7, 2021
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Xilinx / ResNet50-PYNQ

Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ

python xilinx pynq alveo finn

Updated Nov 23, 2021
C++

Xilinx / xup_compute_acceleration

Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware

fpga xilinx vitis xup

Updated Jul 24, 2024
C++

spcl / apfp

FPGA acceleration of arbitrary precision floating point computations.

fpga hls hpc bignum arbitrary-precision high-performance-computing xilinx gmp mpfr high-level-synthesis vivado-hls vitis multiple-precision

Updated May 17, 2022
C++

ECASLab / cynq

PYNQ bindings for C and C++ to avoid requiring Python or Vitis to execute hardware acceleration.

linux fpga runtime amd xilinx pynq artix7 alveo cynq

Updated Jul 15, 2024
C++

jasonlin316 / GCN-Inference-Acceleration-HLS

An end-to-end GCN inference accelerator written in HLS

neural-network hls end-to-end inference xilinx gcn vitis

Updated Apr 5, 2022
C++

brigio345 / DaCH

DaCH: dataflow cache for high-level synthesis.

fpga hls cache xilinx memory-management high-level-synthesis vitis-hls

Updated Jul 27, 2023
C++

Tosainu / ultra96-fractal

Hardware accelerated Julia set explorer running on Ultra96

fpga zynq xilinx vivado systemverilog petalinux julia-sets ultra96

Updated Jul 15, 2024
C++

salehjg / DeepPoint-V2-FPGA

The code repository of DGCNN on FPGA: Acceleration of The Point Cloud Classifier Using FPGAs

fpga deep-learning hls xilinx pointcloud sdaccel shapenet-dataset modelnet-dataset vitis

Updated Mar 6, 2023
C++

petrsocha / hls-crypto

FPGA Cryptography for High-Level Synthesis

Updated Aug 3, 2021
C++

gewuek / flower_classification_vai_tf_dataset

The project show how to quick train a model and deploy it on Xilinx FPGA using TensorFlow and Vitis AI. It uses tf.data.Dataset API to handle input data, so that the input function need to be rewritten. And there is a backup for DNNDK 3.1 tag

python fpga tensorflow xilinx dnndk

Updated Aug 15, 2020
C++

t-kuha / mpsoc-r5

Zynq Ultrascale+ MPSoC RPU examples

zynq xilinx mpsoc rpu cortex-r5

Updated Sep 28, 2024
C++

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