Schematics

The PRO v2.0 schematic, redrawn as two sheets. Same circuit, same reference designators, same pin numbers as the EasyEDA sheets - the difference is that nets are coloured by which side of the level shifters they live on, and the parts that are easy to misread carry a note next to them.

The authoritative source is still the EasyEDA export: pico9918_v2_0_schematic.pdf, alongside the BOM, pick-and-place and Gerbers in pcb/v2.0/. Earlier revisions have their own schematic PDFs in the same place.

Click either sheet to open it full size (ctrl-click or middle-click for a new tab). They are too dense to read at page width.

Reading the sheets

Colour	Meaning
Amber	Host side, 5 V. No suffix: /CSR, CD0, MODE
Teal	MCU side, 3.3 V. _L suffix: /CSR_L, CD0_L
Violet	Analogue video - RGB and sync after the resistor ladder
Red	Supply rail - +5V0, +3V3, +1V1, VDP+5V0, USB+5V0

The _L suffix means the signal at the MCU pin, not a level-shifted host signal. It reads backwards to almost everyone the first time.

Sheet 1 - host interface, level shifting, video out

The host half. H1 to H4 are drawn on the DIP-40 grid they physically occupy, so each pin is labelled with the socket position it lands in. Then the three buffers that stand between a 5 V socket and a 3.3 V part - U6 for control in, U5 for data, U9 for clocks and interrupt out - and on the right the FFC connector with the twelve-resistor RGB ladder.

The /CSR delay chain is called out as a separate inset, because the way it is drawn on the original sheet (three straps crossing the chip body) is almost impossible to follow. See Host Bus Timing for what those extra hops buy.

Sheet 2 - MCU, power, clock, USB

The MCU half. The RP2354A with all sixty pins accounted for, an ideal-diode OR between the two possible 5 V sources, the 3.3 V LDO and the core buck, the 12 MHz crystal, BOOTSEL and the SWD tail. The GPIO map down the right-hand side reads straight across from MCU pin to socket position.

Socket map

The board plugs into a DIP-40 TMS9918A socket. H1 to H4 are four lengths snapped from a single 1x40 2.54 mm male header strip (LCSC C9742) - 24 pins fitted, 16 positions left open, so one strip does one board.

DIP	Header	Net	Connects to
1	H1.2	-	1k pull-up to +5V0 (R21)
2	H1.1	-	1k pull-up to +5V0 (R20)
11	H2.1	MODE1	U6 B0, out at A0 as MODE1_L to GPIO29
12	H2.2	GND
13	H2.3	MODE	U6 B1, out at A1 as MODE_L to GPIO28
14	H2.4	/CSW	U6 B2, out at A2 as /CSW_L to GPIO27
15	H2.5	/CSR	U6 B3, four channels of U6, out at A6 as /CSR_L to GPIO26
16	H2.6	/INT	U9 4Y, driven from /INT_L on GPIO22
17	H2.7	CD7	U5 A0 / B0, CD7_L on GPIO14
18	H2.8	CD6	U5 A1 / B1, CD6_L on GPIO15
19	H2.9	CD5	U5 A2 / B2, CD5_L on GPIO16
20	H2.10	CD4	U5 A3 / B3, CD4_L on GPIO17
21	H3.1	CD3	U5 A4 / B4, CD3_L on GPIO18
22	H3.2	CD2	U5 A5 / B5, CD2_L on GPIO19
23	H3.3	CD1	U5 A6 / B6, CD1_L on GPIO20
24	H3.4	CD0	U5 A7 / B7, CD0_L on GPIO21
33	H4.1	VDP+5V0	board supply, ORed against USB 5 V in U8
34	H4.2	RST	U6 B7, out at A7 as RST_L to GPIO23; also gates /BOE
35	H4.3	-	not connected
36	H4.4	-	not connected
37	H4.5	GROMCLK	U9 1Y through SB2, driven from GROMCLK_L on GPIO25
38	H4.6	CPUCLK	U9 2Y through SB1, driven from CPUCLK_L on GPIO24
39	H4.7	-	not connected
40	H4.8	-	not connected

Positions 3-10 and 25-32 have no pin fitted at all. The board implements the CPU interface only, so the original part's VRAM bus and analogue video pins are simply not connected.

MODE1 on position 11 is not one of the TMS9918A CPU interface pins. It is read like the others but no host drives it as part of a normal bus cycle.

SB1 and SB2 are solder bridges. Cut one to stop the board driving CPUCLK or GROMCLK into a host that already generates its own.

Related

• Hardware - hardware variants, block diagrams and PCB revision history
• Hardware Setup - FFC connector, jumpers and pin configuration
• Host Bus Timing - what the /CSR delay chain and /BOE actually do, cycle by cycle
• TMS9918 Family - the VDPs the PICO9918 replaces