Tapeout Checklist

Tapeout Checklist

Tapeout is the moment the design is released to the foundry. After it, nothing can be changed — a mask set costs real money and a respin costs months. This page is the gate: every item must be checked, evidenced, and signed by a named owner before release.

Treat it as a checklist in the aviation sense. Not a summary of what you probably did, but a list you physically walk through with someone else watching.

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The Golden Rules

1. Freeze before you check. Any change after a check invalidates it.
2. Evidence, not memory. Every item needs an archived log or report.
3. Named owner per item. "The team checked it" means nobody checked it.
4. Two people per critical item. The person who did the work and one who didn't.
5. Waivers are documented or they don't exist. Justification, reviewer, date.
6. If you don't understand it, it isn't signed off.

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Timeline

flowchart LR
    A[Design freeze] --> B[Full signoff run]
    B --> C[Checklist review]
    C --> D[Fix + re-verify]
    D --> C
    C --> E[GDSII release]
    E --> F[Foundry acceptance]
    style C fill:#2d6a9f,color:#fff

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The C → D → C loop is where most tapeouts spend their final weeks. Budget for it — first-pass checklist review always finds something.

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1. Physical Verification

Check	Criterion	Evidence
DRC clean	Zero violations or documented waivers	Pegasus report
LVS clean	No discrepancies	Pegasus report
ERC clean	No floating gates, no supply shorts	Pegasus report
Antenna	Zero violations	Pegasus report
Metal density	Within min/max per layer, fill inserted	Density report
Seal ring	Present and correct per foundry spec	Layout inspection
Scribe / dicing	Correct per shuttle spec	Layout inspection

See Signoff for how these are run.

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2. Timing

Check	Criterion
Setup	WNS ≥ 0, all views, extracted parasitics, SI on
Hold	WNS ≥ 0, all views — no exceptions
Design rules	Zero max_tran, max_cap, max_fanout violations
Analysis coverage	~100%, no silently unconstrained paths
Exceptions reviewed	Every false path and multicycle path justified
All modes	Functional, scan, at-speed all pass
Clock domain crossings	Declared and verified

Hold is non-negotiable — see Timing Closure. A hold violation is a dead chip at every frequency.

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3. Power Integrity

Check	Criterion
Static IR drop	≤ 2–3% VDD
Dynamic IR drop	≤ 5% VDD, with a real activity trace
Electromigration	Within foundry limits for target lifetime
PDN connectivity	Every macro and cell connected; verify_power_via clean
Decap	Inserted, ratio within plan
Power domains	Match UPF; isolation and level shifters correct

See Power Planning.

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4. Functional and Logical

Check	Criterion
LEC	Final netlist equivalent to RTL, all points mapped
Gate-level simulation	Passes with SDF back-annotation
Regression	Full Verification suite green on the tapeout RTL
Reset	Verified from all reset states
Scan chains	Continuity verified, chain order documented
ATPG coverage	Meets target

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5. Chip Integration

Check	Criterion
Padring	Complete, correct pad order, no gaps
Pad assignment	Matches package/bond diagram exactly
ESD	Protection on every pad; correct clamps
Power pads	Sufficient count and distribution for peak current
I/O configuration	Drive strength, pull-ups, levels correct
Corner cells	Present
Bond pad opening	Matches packaging requirement

Pad assignment errors are among the most common and most fatal student-tapeout mistakes. Check it against the bond diagram, pad by pad, with two people.

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6. Deliverables

Item	Notes
GDSII	The layout itself; correct top cell name
LEF	Abstract, if the block is reused
Netlist	Final routed Verilog
SDF	Timing for gate-level simulation
SPEF	Extracted parasitics
Timing reports	All views, archived
DRC/LVS reports	Clean, archived
Waiver document	Every waiver with justification and reviewer
Bond/package diagram	Pad-to-pin mapping
README	How to reproduce the whole flow

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7. Archive and Reproducibility

Archive enough that someone can rebuild this exact database in a year:

• Tool versions (exact, including patch level)
• PDK version and rule deck versions
• All scripts, constraints, and configuration
• Git commit hash of the RTL
• Full logs from every flow stage
• The final database itself

Our chamber pins tool versions deliberately for exactly this reason — record which ones you used.

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8. Process and Sign-off

Item	Owner
Design frozen, no pending ECOs	PD lead
All checklist items evidenced	PD lead
Waivers reviewed and approved	PD lead + advisor
Foundry/shuttle submission requirements met	Integration owner
Submission deadline confirmed	Program owner
Backup of the complete database	Anyone — but verify the backup restores

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Common Tapeout Mistakes

Mistake	Consequence
Late ECO after signoff	Invalidates completed checks; the classic respin cause
Pad assignment mismatch	Chip cannot be bonded correctly — unrecoverable
Hold violation waived under schedule pressure	Dead silicon at every frequency
Signed off on static IR only	Dynamic hotspot fails in the lab
One precision/functional mode unverified	Half the chip untested
Undocumented waiver	Nobody can tell later whether it was safe
Wrong GDS top cell name	Foundry rejects the submission
Missing fill	Density DRC failure at the foundry, after your deadline
No archive	Cannot reproduce or debug the silicon you receive

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Longhorn Silicon Notes

Lambda's chipathon target hardens the decode attention datapath — Q·Kᵀ → softmax → P·V, plus KVE, TIU, and the ACU gate. Specific items to add to the generic list:

• Verify both precision modes. The INT8/FP16 precision controller means two distinct datapath configurations. Timing, power, and functional verification must cover both. Signing off one mode is the highest-risk shortcut available here.
• KVE SRAM connectivity, pin by pin. Macro power/ground pins are a recurring LVS failure. Check every bank explicitly rather than trusting route_special.
• Dynamic IR with a real decode trace. The MatE array's sustained uniform switching is the worst case, and only a realistic workload trace exposes it. Get one from Verification, not a synthetic pattern.
• Clock domain crossings between KVE and the compute array — declared, verified, and covered by STA.
• Array boundary DRC. The operand-broadcast and result-drain regions at MatE's edges are the congested areas from Routing and therefore the likeliest DRC hotspots.
• Metal density across the array. A uniformly dense regular array plus sparse surroundings hits density limits at both ends.
• Reference model parity. Confirm the taped-out RTL still matches the Python golden model. The repo's lab-notebook standard requires this evidence recorded, not asserted.

Student tapeout notes

• The shuttle deadline is immovable. Unlike an internal schedule, a shuttle slot does not slip for you. Work backwards from the submission date and put the signoff freeze at least two weeks earlier than feels necessary.
• GF180MCU submission — the shuttle organiser will run their own DRC/LVS on your GDSII and reject it if unclean. Their acceptance is the real gate, not your local run. Full-chip assembly is in chip/pdk/gf180/.
• Padring first, not last. Pad count and pitch can force the die to grow independently of core area. Discovering this late is a common and expensive student mistake — check it during Floorplanning.
• Do a dry-run tapeout. Take a trivial design — an inverter ring oscillator — all the way through DRC, LVS, and GDS submission format early in the project. It surfaces flow and submission problems while there is still time to fix them, and it is far cheaper than discovering them with the real design.
• Two people, out loud. Walk this checklist with a partner reading items aloud. It catches things silent review does not.

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References

• Foundry / shuttle submission guidelines — the authoritative requirements list; read it early, not at the deadline
• Cadence Pegasus, Tempus, Voltus user guides — how each signoff check is run
• Efabless / SSCS Chipathon documentation — open-shuttle submission requirements and precedents
• SkyWater and GF180MCU PDK documentation — rule decks and required deliverables
• Kahng, Lienig, Markov, Hu — VLSI Physical Design — for the concepts behind each check

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See also: Signoff · Timing Closure · Power Planning · Floorplanning · Physical Design