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Tapeout Checklist
Tapeout is the moment the design is released to the foundry. After it, nothing can be changed — a mask set costs real money and a respin costs months. This page is the gate: every item must be checked, evidenced, and signed by a named owner before release.
Treat it as a checklist in the aviation sense. Not a summary of what you probably did, but a list you physically walk through with someone else watching.
- Freeze before you check. Any change after a check invalidates it.
- Evidence, not memory. Every item needs an archived log or report.
- Named owner per item. "The team checked it" means nobody checked it.
- Two people per critical item. The person who did the work and one who didn't.
- Waivers are documented or they don't exist. Justification, reviewer, date.
- If you don't understand it, it isn't signed off.
flowchart LR
A[Design freeze] --> B[Full signoff run]
B --> C[Checklist review]
C --> D[Fix + re-verify]
D --> C
C --> E[GDSII release]
E --> F[Foundry acceptance]
style C fill:#2d6a9f,color:#fff
The C → D → C loop is where most tapeouts spend their final weeks. Budget for it — first-pass checklist review always finds something.
| Check | Criterion | Evidence |
|---|---|---|
| DRC clean | Zero violations or documented waivers | Pegasus report |
| LVS clean | No discrepancies | Pegasus report |
| ERC clean | No floating gates, no supply shorts | Pegasus report |
| Antenna | Zero violations | Pegasus report |
| Metal density | Within min/max per layer, fill inserted | Density report |
| Seal ring | Present and correct per foundry spec | Layout inspection |
| Scribe / dicing | Correct per shuttle spec | Layout inspection |
See Signoff for how these are run.
| Check | Criterion |
|---|---|
| Setup | WNS ≥ 0, all views, extracted parasitics, SI on |
| Hold | WNS ≥ 0, all views — no exceptions |
| Design rules | Zero max_tran, max_cap, max_fanout violations |
| Analysis coverage | ~100%, no silently unconstrained paths |
| Exceptions reviewed | Every false path and multicycle path justified |
| All modes | Functional, scan, at-speed all pass |
| Clock domain crossings | Declared and verified |
Hold is non-negotiable — see Timing Closure. A hold violation is a dead chip at every frequency.
| Check | Criterion |
|---|---|
| Static IR drop | ≤ 2–3% VDD |
| Dynamic IR drop | ≤ 5% VDD, with a real activity trace |
| Electromigration | Within foundry limits for target lifetime |
| PDN connectivity | Every macro and cell connected; verify_power_via clean |
| Decap | Inserted, ratio within plan |
| Power domains | Match UPF; isolation and level shifters correct |
See Power Planning.
| Check | Criterion |
|---|---|
| LEC | Final netlist equivalent to RTL, all points mapped |
| Gate-level simulation | Passes with SDF back-annotation |
| Regression | Full Verification suite green on the tapeout RTL |
| Reset | Verified from all reset states |
| Scan chains | Continuity verified, chain order documented |
| ATPG coverage | Meets target |
| Check | Criterion |
|---|---|
| Padring | Complete, correct pad order, no gaps |
| Pad assignment | Matches package/bond diagram exactly |
| ESD | Protection on every pad; correct clamps |
| Power pads | Sufficient count and distribution for peak current |
| I/O configuration | Drive strength, pull-ups, levels correct |
| Corner cells | Present |
| Bond pad opening | Matches packaging requirement |
Pad assignment errors are among the most common and most fatal student-tapeout mistakes. Check it against the bond diagram, pad by pad, with two people.
| Item | Notes |
|---|---|
| GDSII | The layout itself; correct top cell name |
| LEF | Abstract, if the block is reused |
| Netlist | Final routed Verilog |
| SDF | Timing for gate-level simulation |
| SPEF | Extracted parasitics |
| Timing reports | All views, archived |
| DRC/LVS reports | Clean, archived |
| Waiver document | Every waiver with justification and reviewer |
| Bond/package diagram | Pad-to-pin mapping |
| README | How to reproduce the whole flow |
Archive enough that someone can rebuild this exact database in a year:
- Tool versions (exact, including patch level)
- PDK version and rule deck versions
- All scripts, constraints, and configuration
- Git commit hash of the RTL
- Full logs from every flow stage
- The final database itself
Pin tool versions deliberately rather than tracking whatever the default resolves to, and record exactly which ones produced the released database.
| Item | Owner |
|---|---|
| Design frozen, no pending ECOs | PD lead |
| All checklist items evidenced | PD lead |
| Waivers reviewed and approved | PD lead + advisor |
| Foundry/shuttle submission requirements met | Integration owner |
| Submission deadline confirmed | Program owner |
| Backup of the complete database | Anyone — but verify the backup restores |
| Mistake | Consequence |
|---|---|
| Late ECO after signoff | Invalidates completed checks; the classic respin cause |
| Pad assignment mismatch | Chip cannot be bonded correctly — unrecoverable |
| Hold violation waived under schedule pressure | Dead silicon at every frequency |
| Signed off on static IR only | Dynamic hotspot fails in the lab |
| One precision/functional mode unverified | Half the chip untested |
| Undocumented waiver | Nobody can tell later whether it was safe |
| Wrong GDS top cell name | Foundry rejects the submission |
| Missing fill | Density DRC failure at the foundry, after your deadline |
| No archive | Cannot reproduce or debug the silicon you receive |
See also: Signoff · Timing Closure · Power Planning · Floorplanning · Physical Design