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[46F_5SP_MMIO] Release v2.0.0

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@T410N T410N released this 21 Dec 09:15
· 20 commits to main since this release
v2.0.0
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Second Major release of basic_RV32s

251221b RV32I46F5SP_MMIO drawio RV32I46F_5SP_MMIO core design's signal-level block diagram. 46F5SP_MMIO_SoC_ drawio 46F5SP_SoC's signal-level block diagram.

Changes

  • Implemented MMIO Interface module in RV32I46F_5SP core
  • Now the core natively supports UART based MMIO.
    (baudrate 115200, LF, UART_TX only)
  • RV32I46F_5SP_MMIO core integrated SoC (46F5SP_MMIO_SoC)
  • 2000 iteration version of Dhrystone 2.1. Implemented on SoC for FPGA; ready to go package
    (For standard iterations that requires at least 2 seconds, Check dhrystone-rv32i-baremetal for more information)

What does this release mean?

  • Previous release executed Dhrystone 2.1 and received results by manually detecting the end of benchmark, receving datas from CSRs.
    (There are some possibilities that we've measured wrong performance data)
  • Now since we've implemented MMIO Interface, we no longer need to receive datas manually, which means the benchmark's result is more reliable than before.
    (We now receive outputs by printf function of dhrystone automatically.)

Informations for the core

  • Memory Map
IMEM(ROM): 0x0000_0000, 16384; 64KB
DMEM(RAM): 0x1000_0000, 8192; 32KB
UART_TX: 0x1001_0000
UART_TX_STATUS: 0x1001_0004
  • UART baudrate is 115200, Line break LF (or AUTO)

What's inside?

  • fpga/
    • Ready to go FPGA project files for Vivado 2024.2
    • Previous v1.0.0's Demo FPGA step-by-step execution debugging project
    • New RV32I46F5SP_MMIO_SoC with Dhrystone 2.1 integration. (2000 iterations)
  • modules/
    • clk_enable signal excluded core only directory for simulation and various uses.
  • testbenches/
    • testbench files for simulating CPU core and submodules in modules/.
    • usage: `./test.sh
    • To use ./test.sh, iverilog is required.

Performance

20251215_141357
46F5SP_MMIO_SoC with RV32I46F_5SP_MMIO core implemented on Digilent Nexys Video FPGA board and ran Dhrystone 2.1.
RV32I46F_5SP_MMIO core implemented 46F5SP_MMIO_SoC was implemented on Digilent Nexys Video board (AMD Xilinx Artix-7 XC7A200T FPGA).
UART baudrate is 115200, line break LF.
FPGA Synthesis and Implementations were done in Vivado 2025.2 and also Vivado 2024.2.
If you are using older version, you can still copy the sources in project file(RV32sDhry_Finale.srcs/) and start a new project or upgrade the Vivado

  • 20ns (50 MHz) timing constraints
  • Synthesis Strategy : Flow_PerfOptimized_high
  • Implementation Strategy : Performance_Explore

Dhrystone performance can be calculated by DMIPS (Dhrystone Million Instructions Per Second).
For standard Dhrystone 2.1 execution, the minimum execution time is 2 seconds.
Thus we've put 300,000 iterations as default without touching the original source code that SiFive Provided, and 2,000 iterations with Too_Small_Time modification on Dhrystone source(Dhry_1.c).

Since we've got the Dhrystones per Second, we can calculate our core's generalized performance through this information.

The proposed performance of RV32I46F_5SP core's dhrystone benchmark is evaluated with the following conditions:

  • 2000 iterations settings (with 300,000 iteration)
  • 50MHz of timing constraints (20ns, clock cycle speed)

In our settings on Digilent Nexys Video FPGA, we obtained:

  • 2,000 iterations : 97,273 Dhrystones per Second

  • 300,000 iterations : 97,087 Dhrystones per Second

  • DMIPS (Dhrystone Million Instructions Per Second)
    1 DMIPS equals to 1757 Dhrystones Per Second.

$$DMIPS_{2,000} = \frac{Dhrystones/sec}{1757} = \frac{97,273}{1757} \approx\, 55.36\, DMIPS$$ $$DMIPS_{300,000} = \frac{Dhrystones/sec}{1757} = \frac{97,087}{1757} \approx\, 55.25\, DMIPS$$
  • DMIPS/MHz
$$\frac{55.25\, DMIPS}{50\, MHz} \approx\; 1.11\, DMIPS/MHz$$

What's Changed

  • [Docs] Update devlog up to 250308 by @T410N in #59
  • [Feat] Implement RV32I43F top module and its testbench by @T410N in #60
  • Revert "[Feat] Implement RV32I43F top module and its testbench" by @ChoiCube84 in #61
  • Update devlog by @ChoiCube84 in #63
  • [Docs] Update devlog up to 250328 by @T410N in #66
  • [Docs] Update devlog by 250412 by @T410N in #67
  • [Docs] Documentation and devlog update by @T410N in #69
  • Update devlog by @ChoiCube84 in #71
  • [Docs] Update devlog up to 250531 about RV32I46F and RV32I46F_5SP's debugging with implementation by @T410N in #114
  • [Docs] Update README and devlog up to 250623 by @T410N in #179
  • [Docs] Revise README file and documents guidelines directory structures by @T410N in #180
  • [Docs] Revise directory structure by @T410N in #182
  • [Feat] Implement RV32I46F_5SP, 46F5SP_SoC design and verify on FPGA by @T410N in #181
  • Integrating documentations made into the main branch by @ChoiCube84 in #183
  • [Feat] Add fpga directory by adding Dhrystone and Demo FPGA verification Vivado project file by @T410N in #184
  • [Docs] Revise guidelines directory by adding annotated_rtl and verify_dhrystone.md by @T410N in #185
  • [Docs] Revise README.md by adding performance evaluation and absolute path notification by @T410N in #186
  • [Docs] Revise README.md by adding FPGA implementation image by @T410N in #187
  • [Docs] Revise basic_rv32s total architecture block diagram by @T410N in #188
  • [Docs] Revised README.md by adding RISC-V Learning Resources listings and missing resoureces by @T410N in #189
  • [Docs] Revise README text arrangement and table of contents link by @T410N in #190
  • [Docs] Update development_log.md's translation from KHWL's raw_devlog by @T410N in #191
  • [Docs] Update debug_log.md up to RV32I46F_5SP's Dhrystone benchmark debugging by @T410N in #192
  • [Chore] Added Clean RTL codes to guideline by @T410N in #193
  • [Feat] Implement MMIO Interface draft and its testbench by @T410N in #194
  • [Hotfix] Revised module/ directory's RTL files by removing clk_enable by @T410N in #196
  • [Docs] Update development log about MMIO design by @T410N in #197
  • Revert "[Feat] Implement MMIO Interface draft and its testbench" by @T410N in #198
  • [Feat] Implement MMIO Interface draft and its testbench by @T410N in #199
  • [Feat] Revise MMIO_Interface module disabling clk_enable logic by @T410N in #200
  • [Feat] Revise Forward Unit about Store hazard forwarding logic by @T410N in #201
  • [Feat] Revsie Hazard Unit about store hazard detection by @T410N in #202
  • [Feat] Revsie Data Memory address bit width 10-bit to 32-bit XLEN by @T410N in #203
  • [Feat] Revise MMIO Interface removing clk_enable logic and its testbench by @T410N in #204
  • [Feat] Revise Instruction Memory adding UART MMIO interface testing scenarios by @T410N in #205
  • [Feat] Revise Hazard Unit removing legacy code about load hazard logic by @T410N in #206
  • [Feat] Revise CSR File about implementing mcycle and minstret CSR and its testbench by @T410N in #207
  • [Feat] Revise CSR File mcycle minstret logic with permission level and its testbench by @T410N in #208
  • [Feat] Revise Control Unit pc_stall logic by @T410N in #209
  • [Feat] Add RV32I46F_5SP_MMIO TOP module draft and its testbench by @T410N in #210
  • [Feat] Implement 46F5SP_MMIO_SoC by @T410N in #211
  • [Feat] Revise Branch Logic misprediction target calculation logic and its testbench by @T410N in #212
  • [Feat] Revise RV32I46F_5SP_MMIO's module instanciation order for better vivado source browsing by @T410N in #213
  • [Feat] Revise Byte Enable Logic Load operation's data offset and its testbench by @T410N in #214
  • [Feat] Revise Data Memory for ROM address access at MEM stage and its testbench by @T410N in #215
  • [Feat] Revise Instruction Decoder opcode logic for better FPGA synthesis by @T410N in #216
  • [Feat] Revise Instruction Memory for ROM address access and its testbench by @T410N in #217
  • [Feat] Implement Unified UART Controller for 46F5SP_MMIO_SoC MMIO UART control by @T410N in #218
  • [FPGA] Implement RV32I46F_5SP_MMIO SoC with Dhrystone 2.1 benchmark by @T410N in #219
  • [Feat] Implement MMIO UART, MMIO CPU core, CSR counters, forwarding & hazard fixes, ROM/RAM mapping and testbenches by @T410N in #220
  • [Docs] Update README and development logs. by @T410N in #221
  • [Docs] Revise README about actual build testing environment and added MMIO core contents. by @T410N in #222
  • [Feat] Revise Instruction Memory by bringing back MISALIGNED STORE LOAD trap handler test scenario by @T410N in #223
  • [Feat] Revise core testbench scenario in Instruction Memory by @T410N in #224
  • [FPGA] Revised RV32I46F5SP_MMIO_Dhrystone project file to 2024.2 vivado compatible by @T410N in #225
  • [Feat] Revise CSR File by removing write enable edge detection buffer logic by @T410N in #226
  • [Docs] Update development log and block diagrams about 46F5SP_MMIO_SoC and the core. by @T410N in #227
  • [FPGA] Update fpga project files from absolute path to relative path by @T410N in #228
  • [Chore] Revise test.sh shell script code structure by @T410N in #229
  • [Feat] Revise CSR File's Edge detection logic and FPGA project file Vivado version compatibility by @T410N in #230

Full Changelog: v1.0.0...v2.0.0

Contributors

T410N and ChoiCube84
Assets 3
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