Ga working 4#12
Open
chick wants to merge 288 commits into
Open
Conversation
Co-authored-by: alonamid <alonamid@eecs.berkeley.edu>
…offchip-axi-setup
Add option to add async queues between chip-serialIO and harness serdes
AXI Memory Over TL Serial Link
Bumps [pygments](https://github.com/pygments/pygments) from 2.2.0 to 2.7.4. - [Release notes](https://github.com/pygments/pygments/releases) - [Changelog](https://github.com/pygments/pygments/blob/master/CHANGES) - [Commits](pygments/pygments@2.2.0...2.7.4) Signed-off-by: dependabot[bot] <support@github.com>
Added info about adding our own sram-macros cache
Edits after review-1
- Remove restore keys comment - fixed typo in echo chipyard-rocket-run-tests.yml - figure out why build-extra-tests fails on second pass
restore exports on run-tests
Use this in chipyard-rocket-run-tests
Use this in chipyard-rocket-run-tests Fixed path to action
Use this in chipyard-rocket-run-tests Fixed path to action
Use this in chipyard-rocket-run-tests Fixed path to action Fixed missing inputs
Use this in chipyard-rocket-run-tests - show working dir in prepare-rtl - use root project dir as cache dir here
removed extra-tests from chipyard-rocket-run-tests use run-tests action
Want to just cache simulation binary common.mk hacked here to defeat rebuild caused by dates on files not cached
Want to just cache simulation binary common.mk hacked here to defeat rebuild caused by dates on files not cached trying to fix weird errro at line 46 in prepare-rtl
Want to just cache simulation binary common.mk hacked here to defeat rebuild caused by dates on files not cached trying to fix weird errro at line 46 in prepare-rtl Needs to have riscv-tools, since we are no longer caching entire repo
Want to just cache simulation binary common.mk hacked here to defeat rebuild caused by dates on files not cached trying to fix weird errro at line 46 in prepare-rtl Needs to have riscv-tools, since we are no longer caching entire repo Is riscv binary present when needed
Want to just cache simulation binary common.mk hacked here to defeat rebuild caused by dates on files not cached trying to fix weird errro at line 46 in prepare-rtl Needs to have riscv-tools, since we are no longer caching entire repo Is riscv binary present when needed Try adding some env vars to get RISCV right
Want to just cache simulation binary common.mk hacked here to defeat rebuild caused by dates on files not cached trying to fix weird errro at line 46 in prepare-rtl Needs to have riscv-tools, since we are no longer caching entire repo Is riscv binary present when needed Try adding some env vars to get RISCV right
Want to just cache simulation binary common.mk hacked here to defeat rebuild caused by dates on files not cached trying to fix weird errro at line 46 in prepare-rtl Needs to have riscv-tools, since we are no longer caching entire repo Is riscv binary present when needed Try adding some env vars to get RISCV right
Want to just cache simulation binary common.mk hacked here to defeat rebuild caused by dates on files not cached trying to fix weird errro at line 46 in prepare-rtl Needs to have riscv-tools, since we are no longer caching entire repo Is riscv binary present when needed Try adding some env vars to get RISCV right missed a couple of sims that were missed in common.mk
Want to just cache simulation binary common.mk hacked here to defeat rebuild caused by dates on files not cached trying to fix weird errro at line 46 in prepare-rtl Needs to have riscv-tools, since we are no longer caching entire repo Is riscv binary present when needed Try adding some env vars to get RISCV right missed a couple of sims that were missed in common.mk Restoring all the other RTL built as part of group-cores Add sims/firesim/sim to path
Time grouping runs (and show key and mapping) Remove setting firrtl log level to info
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
17 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
goal get chipyard-rocket-run-tests and chipyard-hetero-run-tests to both run using cache of prepare-chipyard-cores