v0.6.10

What's Changed

• Add coverage status badge to readme (#270) by @maifeeulasad in #658
• Update coverage.yml by @sfblackl-intel in #661
• trial run for Node v24 by @desmonddak in #660
• keyring-style dart installation rather than holding keys by @desmonddak in #667
• Central synthesizer naming by @desmonddak in #652
• Element, subset, and swizzle collapsing in generated SV by @mkorbel1 in #663
• Collapse adjacent bit selects in swizzles to ranges by @mkorbel1 in #674
• ROHD Hierarchy: an API for compact, generic traversal of a remote design by @desmonddak in #653
• Make slicing a const where all bits equal return a const by @mkorbel1 in #677
• Devtools by @desmonddak in #665
• Configurable SV generation, port object and data types by @mkorbel1 in #678
• Range/range assignment collapsing by @mkorbel1 in #676
• Rohd extension by @desmonddak in #670
• Prevent stack overflow when synthesizing combinational loops by @mkorbel1 in #680
• Add support for preferred radix on Consts by @mkorbel1 in #679
• Optimize constant operations and enforce Const immutability by @mkorbel1 in #682
• Cleaning up dependencies by @mkorbel1 in #688
• Restore SystemVerilog port defaults and add per-direction type configuration by @mkorbel1 in #687
• Return the original signal when replicating by 1 by @aishasalim in #689
• Bump brace-expansion from 5.0.7 to 5.0.9 in /rohd_extension by @dependabot[bot] in #691
• Bump undici from 7.28.0 to 7.29.0 in /rohd_extension by @dependabot[bot] in #692
• Bump fast-uri from 3.1.4 to 3.1.5 in /rohd_extension by @dependabot[bot] in #693
• Preparing to release v0.6.10 by @mkorbel1 in #690

New Contributors

• @sfblackl-intel made their first contribution in #661
• @aishasalim made their first contribution in #689
• @dependabot[bot] made their first contribution in #691

Full Changelog: v0.6.9...v0.6.10