Design Log index

Enigma-NG Design Decision Log

Status: Active Project: Enigma-NG Author: Izzyonstage & GitHub Copilot Version: v.0.1.0 Associated Hardware Revision: Rev A Last Updated: 2026-09-17

This file records key architectural and component decisions made during the design of the Enigma-NG system. Each entry captures the decision taken, the rationale behind it, the alternatives that were considered, and any constraints or caveats that future designers should be aware of.

Entries are numbered sequentially as DEC-NNN. Where a decision supersedes a previous one, the earlier entry is updated with a cross-reference.

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DEC	Title	Date	Status	Summary
[[DEC-001	Design-Log-DEC-001-3v3-enig-used-throughout-3v3-system-removed-from-btb-interconnect]]	3V3_ENIG Used Throughout; 3V3_SYSTEM Removed from BtB Interconnect	2025	Obsolete - superseded by DEC-037
[[DEC-002	Design-Log-DEC-002-poe-option-a2-selected-coilcraft-poe600f-12ld]]	PoE Option A2 Selected: Coilcraft POE600F-12LD	2025	Decided
[[DEC-003	Design-Log-DEC-003-poe-output-12v-or-ing-priority-logic-required]]	PoE Output 12V; OR-ing Priority Logic Required	2025	Decided
[[DEC-004	Design-Log-DEC-004-supercap-charge-current-05a-under-poe]]	Supercap Charge Current 0.5A Under PoE	2025	Superseded by DEC-029 (cell specification updated; 0.5A charge current constraint retained)
[[DEC-005	Design-Log-DEC-005-tps25980-efuse-replaces-tps259474l]]	TPS25980 eFuse Replaces TPS259474L	2025	Decided
[[DEC-006	Design-Log-DEC-006-stusb4500-negotiates-15v5a-75w]]	STUSB4500 Negotiates 15V/5A (75W)	2025	Decided
[[DEC-007	Design-Log-DEC-007-dual-interleaved-lmq61460-q1-5v-buck-12a]]	Dual Interleaved LMQ61460-Q1 5V Buck (12A)	2025	Decided
[[DEC-008	Design-Log-DEC-008-tps25750-emulates-5v5a-pd-profile-to-cm5]]	TPS25750 Emulates 5V/5A PD Profile to CM5	2025	Superseded by DEC-012
[[DEC-009	Design-Log-DEC-009-legacy-controller-probe-access-pin-14-reassigned-to-sw-led-ctrl]]	Legacy Controller Probe-Access Pin 14 Reassigned to SW_LED_CTRL	2025 (GND); superseded by final design (SW_LED_CTRL)	Decided
[[DEC-010	Design-Log-DEC-010-inc-14-deferred-legacy-probe-access-esd-protection-post-prototype]]	INC-14 DEFERRED: Legacy Probe-Access ESD Protection (Post-Prototype)	2025	Deferred - Accepted risk for prototype stage
[[DEC-011	Design-Log-DEC-011-all-power-rails-on-power-module-3v3-enig-serves-rotor-stack]]	All Power Rails on Power Module; 3V3_ENIG Serves Rotor Stack	2025	✔ RESOLVED
[[DEC-012	Design-Log-DEC-012-u4-tps25750-replaced-with-tps25751drefr-nrnd-resolution]]	U4 TPS25750 Replaced with TPS25751DREFR (NRND Resolution)	2026-04-03	✔ RESOLVED
[[DEC-013	Design-Log-DEC-013-l3-emi-inductor-changed-to-bourns-srp1265a-100m]]	L3 EMI Inductor Changed to Bourns SRP1265A-100M	2026-04-03	✔ RESOLVED
[[DEC-014	Design-Log-DEC-014-controller-board-uses-erf8-female-on-both-btb-connectors-for-blind-mate-assembly]]	Controller Board Uses ERF8 (Female) on Both BtB Connectors for Blind-Mate Assembly	2026-04-04	✔ RESOLVED
[[DEC-015	Design-Log-DEC-015-link-beta-connector-reduced-from-80-pin-to-40-pin-erf8-020-erm8-020]]	LINK-BETA Connector Reduced from 80-pin to 40-pin (ERF8-020 / ERM8-020)	2026-04-04	✔ RESOLVED
[[DEC-016	Design-Log-DEC-016-jtag-controlled-impedance-and-series-termination]]	JTAG Controlled Impedance and Series Termination	2026-04-05	✔ ADOPTED
[[DEC-017	Design-Log-DEC-017-minimum-4-layer-stackup-for-all-non-controller-boards]]	Minimum 4-Layer Stackup for All Non-Controller Boards	2026-04-05	✔ ADOPTED
[[DEC-018	Design-Log-DEC-018-connector-pinout-ownership-model]]	Connector Pinout Ownership Model	2026-04-05	Adopted
[[DEC-019	Design-Log-DEC-019-poe-transformer-topology-acf-option-a-selected]]	PoE Transformer Topology: ACF (Option A) Selected	2026-04-05	✔ Adopted
[[DEC-020	Design-Log-DEC-020-gnd-chassis-rib-clearway-enig-bond]]	GND_CHASSIS Rib Clearway ENIG Bond	2026-04-08	Accepted - 2026-04-08
[[DEC-021	Design-Log-DEC-021-supercapacitor-bank-upgrade-2x2-2s2p-2x3-2s3p]]	Supercapacitor Bank Upgrade: 2x2 2S2P → 2x3 2S3P	2026-04-08	Superseded by DEC-029 (arrangement 2S3P retained; cell capacitance updated 22F → 25F Abracon)
[[DEC-022	Design-Log-DEC-022-jdb-ft232h-clock-source-dedicated-12mhz-smd-crystal-selected]]	JDB FT232H Clock Source: Dedicated 12MHz SMD Crystal Selected	2026-04-06	Obsolete - superseded by DEC-037
[[DEC-023	Design-Log-DEC-023-jdb-gnd-chassis-omitted-mounting-holes-tied-to-gnd]]	JDB GND_CHASSIS Omitted; Mounting Holes Tied to GND	2026-04-06	Decided
[[DEC-024	Design-Log-DEC-024-jdb-is-complete-jtag-master-controller-jtag-lines-are-pass-through]]	JDB is Complete JTAG Master; Controller JTAG Lines Are Pass-Through	2026-04-06	Decided
[[DEC-025	Design-Log-DEC-025-cm5-shutdown-mechanism-hardware-driven-ltc3350-software-support-deferred]]	CM5 Shutdown Mechanism: Hardware-Driven; LTC3350 Software Support Deferred	2026-04-09	Deferred - Software PoC Stage
[[DEC-026	Design-Log-DEC-026-rotor-position-encoder-as5600-replaced-with-single-track-capacitive-encoder]]	Rotor Position Encoder: AS5600 Replaced with Single-Track Capacitive Encoder	2026-04-12	Accepted
[[DEC-027	Design-Log-DEC-027-rotor-position-readback-via-jtag-virtual-jtag-user0-udr]]	Rotor Position Readback via JTAG Virtual JTAG (USER0 UDR)	2026-04-12	Accepted
[[DEC-028	Design-Log-DEC-028-split-dual-board-rotor-architecture]]	Split dual-board rotor architecture	2026-04-14	Accepted
[[DEC-029	Design-Log-DEC-029-supercapacitor-hold-up-specification-25f-abracon-cells-2s4p-20-s-at-15w]]	Supercapacitor Hold-Up Specification: 25F Abracon Cells, 2S4P, ≥20 s at 15W	2026-04-14	Accepted - 2026-04-14
[[DEC-030	Design-Log-DEC-030-5v-main-backup-switchover-transient-fix-r14-r30-c35]]	5V_MAIN Backup Switchover Transient Fix (R14, R30, C35)	2026-04-14	Accepted
[[DEC-031	Design-Log-DEC-031-cm5-virtual-keyboard-key-injection-feature-architecture]]	CM5 Virtual Keyboard (Key Injection) Feature Architecture	2026-04-14	Decided
[[DEC-032	Design-Log-DEC-032-settings-board-panel-mount-configuration-controls-with-cm5-override]]	Settings Board: Panel-Mount Configuration Controls with CM5 Override	2026-04-14	Decided
[[DEC-033	Design-Log-DEC-033-dsi1-display-connector-provision-for-optional-lid-touchscreen]]	DSI1 Display Connector Provision for Optional Lid Touchscreen	2026-04-14	Decided
[[DEC-034	Design-Log-DEC-034-switch-hardware-refresh-settings-board-toggle-discrete-rgb-led-ruggedized-pm-sw1]]	Switch Hardware Refresh: Settings Board Toggle + Discrete RGB LED, Ruggedized PM SW1	2026-04-16	Decided
[[DEC-035	Design-Log-DEC-035-hid-keyboard-and-lightboard-use-a-40-position-qwerty-derived-layout-for-the-64-character-code-space]]	HID Keyboard and Lightboard Use a 40-Position QWERTY-Derived Layout for the 64-Character Code Space	2026-04-17	Decided
[[DEC-036	Design-Log-DEC-036-link-beta-former-monitor-pins-reallocated-as-grouped-power-rails]]	LINK-BETA Former Monitor Pins Reallocated as Grouped Power Rails	2026-04-18	Decided
[[DEC-037	Design-Log-DEC-037-link-beta-pin-map-regrouped-around-dedicated-jtag-and-i2c-guard-bands]]	LINK-BETA Pin Map Regrouped Around Dedicated JTAG and I2C Guard Bands	2026-04-18	Decided
[[DEC-038	Design-Log-DEC-038-controller-centric-dock-architecture-replaces-legacy-link-alpha-link-beta-backplane]]	Controller-Centric Dock Architecture Replaces Legacy Link-Alpha / Link-Beta Backplane	2026-04-19	Decided
[[DEC-039	Design-Log-DEC-039-enclosure-connected-boards-use-gnd-chassis-daughterboards-are-exempt]]	Enclosure-Connected Boards Use GND_CHASSIS; Daughterboards Are Exempt	2026-04-20	Decided
[[DEC-040	Design-Log-DEC-040-diagnostics-banks-removed-from-active-design-specs-pending-coupon-review]]	Diagnostics Banks Removed from Active Design Specs Pending Coupon Review	2026-04-25	Decided
[[DEC-041	Design-Log-DEC-041-encoder-modules-use-epm570-with-digital-debounce-and-role-by-programming]]	Encoder Modules Use EPM570 with Digital Debounce and Role-by-Programming	2026-04-26	Decided
[[DEC-042	Design-Log-DEC-042-encoder-port-pin-8-carries-hid-local-enc-active-n]]	Encoder Port Pin 8 Carries HID-Local ENC_ACTIVE_N	2026-04-26	Decided
[[DEC-043	Design-Log-DEC-043-shared-actuation-module-replaces-direct-controller-servo-gpio]]	Shared Actuation Module Replaces Direct Controller Servo GPIO	2026-04-26	Decided
[[DEC-044	Design-Log-DEC-044-fdc2114-internal-oscillator-selected-clkin-gnd]]	FDC2114 Internal Oscillator Selected (CLKIN → GND)	2026-04-26	Decided
[[DEC-045	Design-Log-DEC-045-rotor-samtec-erm8erf8-connectors-require-esd-protection]]	Rotor Samtec ERM8/ERF8 Connectors Require ESD Protection	2026-04-28	Decided
[[DEC-046	Design-Log-DEC-046-bypassdecoupling-capacitor-voltage-rating-50v-retained-on-all-non-pm-boards]]	Bypass/Decoupling Capacitor Voltage Rating: 50V Retained on All Non-PM Boards	2026-04-29	Decided
[[DEC-047	Design-Log-DEC-047-or-ing-mosfet-corrected-to-csd17578q5a]]	OR-ing MOSFET Corrected to CSD17578Q5A	2025-07-05	Decided
[[DEC-048	Design-Log-DEC-048-esd-protection-extended-to-host-side-rotor-facing-btb-connectors]]	ESD Protection Extended to Host-Side Rotor-Facing BtB Connectors	2026-04-30	Approved
[[DEC-049	Design-Log-DEC-049-rotor-internal-headers-renamed-to-j-convention-connector-count-updated-to-8-bom-unified]]	Rotor Internal Headers Renamed to J-Convention; Connector Count Updated to 8; BOM Unified	2026-05-01	Accepted
[[DEC-050	Design-Log-DEC-050-encoder-blade-terminal-refdes-corrected-from-bt-to-j-convention]]	Encoder Blade Terminal RefDes Corrected from BT to J Convention	2026-05-01	Active
[[DEC-051	Design-Log-DEC-051-settings-board-renamed-to-user-settings-module-board-code-sbd-usm]]	Settings Board Renamed to User Settings Module (Board Code SBD → USM)	2026-05-02	Active
[[DEC-052	Design-Log-DEC-052-variant-specific-fdc2114-refdes-use-ab-suffix-convention]]	Variant-Specific FDC2114 RefDes Use A/B Suffix Convention	2025-07-10	Active
[[DEC-053	Design-Log-DEC-053-extension-port-connector-upgraded-from-bhr-20-vua-20-pin-to-2bhr-30-vua-30-pin]]	Extension Port Connector Upgraded from BHR-20-VUA (20-pin) to 2BHR-30-VUA (30-pin)	2025-07-10	Active
[[DEC-054	Design-Log-DEC-054-signal-net-renamed-pwr-but-pwr-but-n-active-low-suffix-conformance]]	Signal Net Renamed: PWR_BUT → PWR_BUT_N (Active-Low Suffix Conformance)	2026-07-11	Active
[[DEC-055	Design-Log-DEC-055-f-108-system-wide-reference-designator-and-requirement-id-consecutive-renumbering]]	F-108 System-Wide Reference Designator and Requirement ID Consecutive Renumbering	2026-05-05	Accepted
[[DEC-056	Design-Log-DEC-056-relocate-investigation-documents-to-board-owned-folders]]	Relocate Investigation Documents to Board-Owned Folders	2026-05-04	Accepted
[[DEC-057	Design-Log-DEC-057-daughterboard-mounting-hole-specification-and-standoff-bom-ownership]]	Daughterboard Mounting Hole Specification and Standoff BOM Ownership	2026-05-05	Accepted
[[DEC-058	Design-Log-DEC-058-jdb-connector-upgrade-hat-headers-to-df40c-20-btb]]	JDB Connector Upgrade: Hat-Headers to DF40C-20 BtB	2026-05-15	Accepted
[[DEC-059	Design-Log-DEC-059-erm8erf8-stacking-height-confirmed-rotor-stack-assembly-specification-created]]	ERM8/ERF8 Stacking Height Confirmed; Rotor Stack Assembly Specification Created	2026-05-28	Confirmed
[[DEC-060	Design-Log-DEC-060-jtag-daughterboard-renamed-to-jtag-module-jdb-prefix-replaced-with-jm]]	JTAG Daughterboard Renamed to JTAG Module; JDB Prefix Replaced with JM	2026-05-07	Confirmed
[[DEC-061	Design-Log-DEC-061-pass-7-review-corrections-ctlstarotencamgrsstatus-updates]]	Pass 7 Review Corrections: CTL/STA/ROT/ENC/AM/GRS/Status Updates	2026-05-08	Confirmed
[[DEC-062	Design-Log-DEC-062-ctl-poe-t1-selection-tdk-b82806d0060a120-topology-acf-flyback-acf-forward]]	CTL PoE T1 Selection: TDK B82806D0060A120; Topology ACF Flyback → ACF Forward	2025-07-10	Confirmed
[[DEC-063	Design-Log-DEC-063-ctl-poe-l1-selection-yageo-pa4343333nlt-acf-forward-output-inductor]]	CTL PoE L1 Selection: Yageo PA4343.333NLT (ACF Forward Output Inductor)	2026-05-09	Confirmed
[[DEC-064	Design-Log-DEC-064-ctl-poe-c17-final-part-selection-kemet-c0805c223k2racauto-22nf-200v-x7r-0805]]	CTL PoE C17 Final Part Selection: Kemet C0805C223K2RACAUTO (22nF 200V X7R 0805)	2026-05-09	Confirmed
[[DEC-065	Design-Log-DEC-065-system-wide-stackup-code-correction-and-jlcpcb-authoritative-impedance-values]]	System-Wide Stackup Code Correction and JLCPCB-Authoritative Impedance Values	2026-05-11	Confirmed
[[DEC-066	Design-Log-DEC-066-grs-canonical-pcb-stackup-authority-consolidation]]	GRS Canonical PCB Stackup Authority (Consolidation)	2026-05-11	Confirmed
[[DEC-067	Design-Log-DEC-067-am-sw1sw2-tactile-switch-rating-accepted-for-production]]	AM SW1/SW2 Tactile Switch Rating Accepted for Production	2026-05-12	Confirmed
[[DEC-068	Design-Log-DEC-068-pm-per-input-bulk-capacitors-and-output-source-quality-bulk-banks]]	PM Per-Input Bulk Capacitors and Output Source-Quality Bulk Banks	2026-05-12	Confirmed
[[DEC-069	Design-Log-DEC-069-pm-per-input-polyfuse-protection-and-uvlo-resistor-recalculation]]	PM Per-Input Polyfuse Protection and UVLO Resistor Recalculation	2026-05-14	Confirmed
[[DEC-070	Design-Log-DEC-070-mcp23017-i²c-silicon-restriction-gpb7gpa7-review-and-cfg-apply-n-reassignment]]	MCP23017 I²C Silicon Restriction: GPB[7]/GPA[7] Review and CFG_APPLY_N Reassignment	2026-05-13	Confirmed
[[DEC-071	Design-Log-DEC-071-usm-spdt-switch-dual-terminated-wiring-and-pull-down-resistor-removal]]	USM SPDT Switch Dual-Terminated Wiring and Pull-Down Resistor Removal	2026-05-14	Confirmed
[[DEC-072	Design-Log-DEC-072-review-pass-9-findings-and-resolutions]]	Review Pass 9 Findings and Resolutions	2026-05-14	Accepted
[[DEC-073	Design-Log-DEC-073-ltc3350-rt-resistor-correction-332-kω-133-kω-amends-dec-030]]	LTC3350 RT Resistor Correction: 33.2 kΩ → 133 kΩ (Amends DEC-030)	2026-05-15	Accepted
[[DEC-074	Design-Log-DEC-074-rename-cpld-reset-signal-sys-reset-n-cpld-reset-n]]	Rename CPLD Reset Signal: SYS_RESET_N → CPLD_RESET_N	2026-05-16	Accepted
[[DEC-075	Design-Log-DEC-075-tps25751-option-c-external-eeprom-isolated-i2ct-debug-header-on-power-module]]	TPS25751 Option C: External EEPROM + Isolated I2Ct Debug Header on Power Module	2026-05-16	Accepted
[[DEC-076	Design-Log-DEC-076-pm-3v3-architecture-redesign-3v3-main3v3-enig-rail-split-j4-dual-purpose-programming-j6-removal-and-q12-parallel-p-fet-selection]]	PM 3V3 Architecture Redesign: 3V3_MAIN/3V3_ENIG Rail Split, J4 Dual-Purpose Programming, J6 Removal, and Q12 Parallel P-FET Selection	2026-05-16	Accepted
[[DEC-077	Design-Log-DEC-077-retrospective-rotor-ttd-daisy-chain-no-series-termination-resistors-amends-dec-016]]	Retrospective: Rotor TTD Daisy-Chain - No Series Termination Resistors (Amends DEC-016)	2026-05-18	Accepted
[[DEC-078	Design-Log-DEC-078-cpld-reset-n-stator-buffer-bss138-n-channel-mosfet-new-decision-references-dec-077]]	CPLD_RESET_N Stator Buffer: BSS138 N-Channel MOSFET (New Decision; References DEC-077)	2026-05-18	Accepted
[[DEC-079	Design-Log-DEC-079-c20-voltage-rating-correction-25v-35v-amends-dec-072-bom-item-1]]	C20 Voltage Rating Correction: 25V → 35V (Amends DEC-072 BOM Item 1)	2026-05-18	Accepted
[[DEC-080	Design-Log-DEC-080-retrospective-pm-and-stator-dock-connector-redesignation-amends-dec-038]]	Retrospective: PM and Stator Dock Connector Redesignation (Amends DEC-038)	2026-05-18	Decided
[[DEC-081	Design-Log-DEC-081-retrospective-rotor-ttd-no-series-resistor-policy-in-addition-to-dec-016]]	Retrospective: Rotor TTD No-Series-Resistor Policy (In Addition to DEC-016)	2026-05-18	Decided
[[DEC-082	Design-Log-DEC-082-10µf-bulk-reservoir-capacitor-upgrade-25v-0805-50v-1206-all-boards]]	10µF Bulk Reservoir Capacitor Upgrade: 25V 0805 → 50V 1206, All Boards	2026-05-21	Confirmed
[[DEC-083	Design-Log-DEC-083-retire-all-boards-bomjson-consolidate-bom-authority-in-design-spec-files-and-consolidated-bom]]	Retire all_boards_bom.json; Consolidate BOM Authority in Design_Spec Files and Consolidated_BOM	2026-05-21	Confirmed
[[DEC-084	Design-Log-DEC-084-cypher-stack-architecture-migration-and-board-role-consolidation]]	Cypher-Stack Architecture Migration and Board-Role Consolidation	2026-07-04	Confirmed
[[DEC-085	Design-Log-DEC-085-stack-output-j4-power-pin-zero-ohm-links-prototype-test]]	Stack-Output J4 Power-Pin 0Ω Links for Prototype Test Flexibility	2026-07-12	Accepted — confirm after prototype testing
[[DEC-086	Design-Log-DEC-086-cypher-input-common-variant-restructure-10-numeric-variant-single-i2c-address]]	Cypher-Input Restructured into Common/Variant Files; 10-Numeric Variant Added; Single Shared I2C Address	2026-08-12	Decided
[[DEC-087	Design-Log-DEC-087-cypher-input-led-colour-architecture-moved-off-plain-bits-onto-local-rgb-select-circuit]]	Cypher-Input LED Colour Architecture Moved Off plain-bits, Onto a Local RGB Colour-Select Circuit	2026-08-14	Decided
[[DEC-088	Design-Log-DEC-088-plugboard-jacks-wired-directly-to-cypher-board-spade-bank-j4j6-reserves-5v-main]]	Plugboard Jacks Wired Directly to Cypher Board Spade Bank; J4/J6 Left Pair Reserves 5V_MAIN	2026-08-16	Decided
[[DEC-089	Design-Log-DEC-089-board-role-id-widened-to-4-bit-capability-bitmask-cpld-pin-freeing-and-j5-migration]]	BOARD_ROLE_ID Widened to 4-Bit Capability Bitmask; CPLD Pin-Freeing via JTAG UFM Write; Migration to J5	2026-08-16	Decided
[[DEC-090	Design-Log-DEC-090-cypher-board-j3-stack-input-side-full-50-pin-allocation-and-actuate-request-in-out-n-signal-pair]]	Cypher Board J3 (Stack-Input Side) Full 50-Pin Allocation; ACTUATE_REQUEST_IN_N/ACTUATE_REQUEST_OUT_N Signal Pair	2026-09-01	Decided
[[DEC-091	Design-Log-DEC-091-j3-esd-protection-extended-to-actuate-request-pins-and-actuation-gating-resolved-to-cypher-cpld]]	J3 ESD Protection Extended to ACTUATE_REQUEST_IN_N/OUT_N; Actuation Gating Resolved to Cypher CPLD (Amends DEC-090)	2026-09-01	Decided
[[DEC-092	Design-Log-DEC-092-cypher-board-j4-stack-output-side-full-50-pin-allocation]]	Cypher Board J4 (Stack-Output Side) Full 50-Pin Allocation	2026-09-02	Decided
[[DEC-093	Design-Log-DEC-093-actuate-request-end-to-end-signal-path-j4-rename-rotor-interposer-connectors-extended]]	ACTUATE_REQUEST End-to-End Signal Path Defined; J4 Renamed to REF-Specific Nets; Rotor/Stack-Interposer Connectors Extended	2026-09-02	Decided
[[DEC-094	Design-Log-DEC-094-connector-ownership-reassignment-for-reused-chain-templates]]	Connector Ownership Reassignment for Reused Chain Templates (Amends DEC-018)	2026-09-02	Decided
[[DEC-095	Design-Log-DEC-095-actuate-request-esd-protection-completed-stack-output-passive-wiring-defined]]	ACTUATE_REQUEST ESD Protection Completed (Stack-Input, Stack-Output); Stack-Output Passive Wiring Defined	2026-09-02	Decided
[[DEC-096	Design-Log-DEC-096-stack-blanking-board-corrected-actuate-request-bridging-added]]	Stack-Blanking Board Corrected: ENC_ACTIVE_N/ACTUATE_REQUEST_N Termination Removed; ACTUATE_REQUEST Bridging Added	2026-09-02	Decided
[[DEC-097	Design-Log-DEC-097-cypher-j3-actuate-request-out-n-wired-as-round-trip-verification-input]]	Cypher J3 ACTUATE_REQUEST_OUT_N Wired to CPLD as Round-Trip Verification Input	2026-09-02	Decided
[[DEC-098	Design-Log-DEC-098-controller-cypher-dock-split-power-molex-signal-samtec-amends-dec-038-dec-080]]	Controller ↔ Cypher Dock Split: Power-Only Molex + Signal-Only Samtec (Amends DEC-038, DEC-080)	2026-09-04	Decided
[[DEC-099	Design-Log-DEC-099-cm5-i2c-bank-architecture-mipi0-to-mipi1-swap-pwm-gpclk-reservation]]	CM5 I2C Bank Architecture (I2C0 PM-Dedicated + I2C1-I2C6 via Cypher), MIPI0→MIPI1 Swap, PWM/GPCLK Reservation	2026-09-04	Decided
[[DEC-100	Design-Log-DEC-100-jtag-module-actuation-module-retirement-from-controller-board]]	JTAG Module and Actuation Module Retirement from Controller Board	2026-09-04	Decided
[[DEC-101	Design-Log-DEC-101-cypher-ina219-i2c-address-aligned-to-pm-default]]	Cypher Board INA219 I2C Address Aligned to PM Default (0x45 → 0x40)	2026-09-08	Decided
[[DEC-102	Design-Log-DEC-102-cypher-ft232h-3v3-vregin-self-powered-5v-usb-net-retired]]	Cypher FT232H Moved to 3.3V VREGIN Self-Powered Operation (5V_USB Net Retired)	2026-09-11	Decided

| DEC-103 | HID / USM Hub Connector Topology Rework | 2026-09-17 | Decided | Retires the HID boards' former right-pair J5/J7 chain-through connectors, adds a dedicated USM-facing right-edge connector on both HID boards, repurposes Cypher J6 as the USM hub, and repurposes Cypher-Plugboard J2 to mate USM rather than a HID board. | | DEC-104 | User Settings Module Reworked as HID Colour / Audio Hub and JTAG/I2C Spine | 2026-09-17 | Decided | USM is now the shared HID lighting-colour / brightness hub, the placeholder audio board, and the JTAG / I2C spine between Cypher and the HID boards. CFG_ROUTE and panel-switch behaviour are removed from USM. | | DEC-105 | CFG_ROUTE Moved to Full CM5 Software Control; Physical USM Switches Retired | 2026-09-17 | Decided | CFG_ROUTE[3:0] is now CM5-owned only. The physical USM switch and apply-button path is removed. CFG_REFMAP remains governed by DEC-089's JTAG UFM write decision. | | DEC-106 | Cypher-Plugboard Reduced to Mechanical / Connector-Only Board | 2026-09-17 | Decided | Cypher-Plugboard now carries only the two board-to-board connectors and no active electrical components. The plugboard jack field remains mechanically mounted and harnessed directly to Cypher J20+. | | DEC-107 | USM/HID Connector Four-Colour-Style Signal Expansion | 2026-09-21 | Decided | Template 3 (USM-to-HID connector) expanded from a single generic LED colour/brightness signal group to 4 independent colour-style groups, letting a HID board's own local logic access more than one stored colour value simultaneously. USM's colour-value store expands to 4 styles (3 used initially, 1 reserved). |