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Electronics Stack Interposer Design Spec
github-actions[bot] edited this page Oct 15, 2026
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Status: Draft Project: Enigma-NG Author: Izzyonstage & GitHub Copilot Version: v.0.1.0 Associated Hardware Revision: Rev A Last Updated: 2026-09-02
The Stack-Interposer Board is a passive rigid bridge board that sits horizontally at the base of each Rotor Mini-Stack. It mechanically and electrically connects the bottom edge of the Stack-Output Board (J6) to the bottom edge of the Stack-Input Board (J6), completing the intra-stack signal return path without requiring a flexible ribbon cable.
| Responsibility | Description |
|---|---|
| Signal bridge | Routes SIG-BLOCK-A (ENC_DATA[5:0] forward), SIG-BLOCK-D (ENC_DATA[5:0] return direction), SIG-BLOCK-E (TTD), and SIG-BLOCK-G/H (ACTUATE_REQUEST forward/return, per DEC-093) between the Stack-Output Board and the Stack-Input Board via passive pin-to-pin trace connections |
| GND shielding | Interleaved GND contacts on both connectors isolate every signal line; GND pours on L1 and L4 provide plane-level EMI shielding |
| Mechanical rigidity | Rigid PCB-to-PCB join stiffens the mini-stack base, making the mini-stack assembly self-supporting without a flexible ribbon cable |
The board carries two straight/vertical 30-contact 2×15 connectors on its top surface: J1 mates with Stack-Output Board J6 (bottom edge) and J2 mates with Stack-Input Board J6 (bottom edge). Stack-Output and Stack-Input carry right-angle connectors on their bottom edges; the Stack-Interposer uses straight (vertical) connectors since it lies horizontal at the base with the two vertical boards rising on either side.
System configuration: One Stack-Interposer Board is required per Rotor Mini-Stack (up to 6 per system — 30 rotor positions total). The board has no function in isolation.
| ID | Functional Requirement | Notes | Satisfied By / Cross-Ref |
|---|---|---|---|
| FR-SINT-01 | Provide a rigid mechanical and electrical bridge between the Stack-Output Board J6 (bottom edge) and the Stack-Input Board J6 (bottom edge) within each Rotor Mini-Stack | Replaces flexible ribbon cable; mechanically stiffens the mini-stack base | §4 Interconnects; BOM J1, J2 |
| FR-SINT-02 | Route SIG-BLOCK-A (ENC_DATA[5:0] forward) from Stack-Output Board J6 to Stack-Input Board J6 as a passive pin-to-pin connection | Forward-direction ENC data from last ROT board output; passed to Stack-Input for onward chain or blanking board handoff | §3 Signal Routing; BOM J1, J2 |
| FR-SINT-03 | Route SIG-BLOCK-D (ENC_DATA[5:0] return direction) from Stack-Input Board J6 to Stack-Output Board J6 as a passive pin-to-pin connection | Return-direction ENC data (post-reflector) entering Stack-Output ROT chain for left-to-right return traversal | §3 Signal Routing; BOM J1, J2 |
| FR-SINT-04 | Route SIG-BLOCK-E (TTD) from Stack-Output Board J6 to Stack-Input Board J6 as a passive pin-to-pin connection | Last ROT board TDO output; forwarded to Stack-Input for onward JTAG chain or blanking board handoff; TTD carried on two pins (13 and 18) with guard GND between | §3 Signal Routing; Board_Layout.md §3 |
| FR-SINT-05 | Provide interleaved GND contacts between all signal pairs on both connectors per the 2×15 pin map | One GND contact adjacent to each signal line; single guard GND remaining at SIG-BLOCK-E/G/H centre (pin 17) after DEC-093 | §3 Signal Routing; Board_Layout.md §3 |
| FR-SINT-06 | Route SIG-BLOCK-G (ACTUATE_REQUEST forward) from Stack-Output Board J6 to Stack-Input Board J6 as a passive pin-to-pin connection | Actuation-trigger forward pass, collected from this mini-stack's own Rotor chain via Stack-Output; forwarded to Stack-Input's rear connector | §3 Signal Routing; BOM J1, J2 |
| FR-SINT-07 | Route SIG-BLOCK-H (ACTUATE_REQUEST return) from Stack-Input Board J6 to Stack-Output Board J6 as a passive pin-to-pin connection | Actuation-trigger return pass, received on Stack-Input's rear connector; routed back through this mini-stack's Rotor chain via Stack-Output in reverse | §3 Signal Routing; BOM J1, J2 |
| ID | Design Requirement | Specification | Satisfied By / Cross-Ref |
|---|---|---|---|
| DR-SINT-01 | PCB stackup | 4-layer per design/Standards/Global_Routing_Spec.md §2.3.1; GND pour on L1 (top) and L4 (bottom) for EMI shielding; all signal routing on L2 and L3 only |
§5 PCB Fabrication & Stackup |
| DR-SINT-02 | J1 — Stack-Output side mating connector | J1 = TMMH-115-01-L-D-ES (Samtec 30-position 2×15 straight/vertical male); mates with Stack-Output Board J6 (SQT-115-01-L-D-RA right-angle female) on the Stack-Output bottom edge; pin map defined in Board_Layout.md §3
|
§4 Interconnects; BOM J1 |
| DR-SINT-03 | J2 — Stack-Input side mating connector | J2 = TMMH-115-01-L-D-ES (Samtec 30-position 2×15 straight/vertical male); mates with Stack-Input Board J6 (SQT-115-01-L-D-RA right-angle female) on the Stack-Input bottom edge; pin map defined in Board_Layout.md §3
|
§4 Interconnects; BOM J2 |
| DR-SINT-04 | Pin map — pin-to-pin with mirror-aware trace routing | J1 pin n connects to J2 pin n (pin-to-pin passive continuity); no buffering or signal conditioning. Because J1 and J2 face upward with their pin-1 ends facing each other (Stack-Output and Stack-Input approach from opposite sides), the physical trace routes on L2 and L3 will need to be laid out as if mirrored — traces will cross as they route across the board. Rows are preserved (row 1 → row 1, row 2 → row 2). Signal assignments per connector defined in Board_Layout.md §3
|
§3 Signal Routing; §5 PCB Fabrication; Board_Layout.md §3 |
| DR-SINT-05 | Mounting holes | MH1–MH4: M3 PTH (3.2mm drill) tied to GND_CHASSIS per GRS §4. No BOM entry. | §5 PCB Fabrication |
| DR-SINT-06 | Signal trace width | All signal traces on L2/L3 routed at CI width per design/Standards/Global_Routing_Spec.md §2.3.1, targeting 50 Ω controlled impedance |
§5 PCB Fabrication |
| DR-SINT-07 | System quantity | 1 per Rotor Mini-Stack; up to 6 per system (30 rotor positions total) | §1 Overview |
flowchart LR
subgraph J1side["J1 — Stack-Output Side"]
J1["J1 TMMH-115-01-L-D-ES\nStraight/vertical male\nMates with Stack-Output J6 (SQT-115-01-L-D-RA)"]
end
subgraph J2side["J2 — Stack-Input Side"]
J2["J2 TMMH-115-01-L-D-ES\nStraight/vertical male\nMates with Stack-Input J6 (SQT-115-01-L-D-RA)"]
end
J1 -- "SIG-BLOCK-A: ENC_DATA[5:0] fwd" --> J2
J2 -- "SIG-BLOCK-D: ENC_DATA[5:0] return" --> J1
J1 -- "SIG-BLOCK-E: TTD (pins 13 + 18)" --> J2
J1 -- "SIG-BLOCK-G: ACTUATE_REQUEST fwd (pin 15)" --> J2
J2 -- "SIG-BLOCK-H: ACTUATE_REQUEST return (pin 16)" --> J1
-
PCB: 4-layer per
design/Standards/Global_Routing_Spec.md §2.3.1. ENIG Gold. 2.0mm filleted corners. - Assembly: Single-sided; passive components only (2× connectors).
- Orientation: Mounted horizontally at the base of the Rotor Mini-Stack. Stack-Output Board and Stack-Input Board stand vertically on either side with their right-angle J6 bottom-edge connectors mating down into the Stack-Interposer's upward-facing J1 and J2.
- Manufacturer: JLCPCB (standard 4-layer).
Per GRS §5: local GND_CHASSIS net tied to mounting holes; no local GND to GND_CHASSIS bond.
System's only galvanic bond remains on the Power Module.
This board is passive: all signals pass through as direct trace connections between J1 (Stack-Output side) and J2 (Stack-Input side). No buffering, level shifting, or conditioning.
| Signal Block | Signals | Direction | Notes |
|---|---|---|---|
| SIG-BLOCK-A | ENC_DATA[5:0] | J1 → J2 | Forward-direction ENC data from last ROT board; forwarded to Stack-Input for next-stack or blanking board handoff |
| SIG-BLOCK-D | ENC_DATA[5:0] | J2 → J1 | Return-direction ENC data post-reflector; received from Stack-Input; enters Stack-Output ROT chain for left-to-right return traversal |
| SIG-BLOCK-E | TTD | J1 → J2 | Last ROT board TDO output; forwarded to Stack-Input for next-stack or blanking board handoff; carried on pins 13 and 18 |
| SIG-BLOCK-G | ACTUATE_REQUEST | J1 → J2 | Actuation-trigger forward pass, collected from this mini-stack's own Rotor chain via Stack-Output; forwarded to Stack-Input's rear connector; carried on pin 15. Per DEC-093. |
| SIG-BLOCK-H | ACTUATE_REQUEST | J2 → J1 | Actuation-trigger return pass, received on Stack-Input's rear connector; routed back through this mini-stack's Rotor chain via Stack-Output in reverse; carried on pin 16. Per DEC-093. |
The signal assignment is pin-to-pin: J1 pin n connects to J2 pin n. Signal assignments per
connector are defined in Board_Layout.md §3.
Due to the physical orientation of the assembly — J1 (Stack-Output side) and J2 (Stack-Input side) both face upward, with the two mating boards approaching from opposite sides — the pin-1 ends of J1 and J2 face each other. As a result, the L2 and L3 trace routes will need to be laid out as if mirrored: traces will cross as they run across the board between J1 and J2. The rows are preserved (row 1 → row 1, row 2 → row 2). This is a PCB routing constraint, not a change to the electrical pin mapping.
The 30 contacts are grouped as follows:
- Pins 1–12 (SIG-BLOCK-A): ENC_DATA[5:0] forward direction, interleaved with GND — one signal per odd/even pair alternating (signal, GND, GND, signal, ...).
-
Pins 13–18 (SIG-BLOCK-E/G/H): TTD carried on both pins 13 and 18;
ACTUATE_REQUESTforward (SIG-BLOCK-G) on pin 15 and return (SIG-BLOCK-H) on pin 16, per DEC-093; single guard GND remaining on pin 17. - Pins 19–30 (SIG-BLOCK-D): ENC_DATA[5:0] return direction, interleaved with GND in the same alternating pattern as SIG-BLOCK-A but bit-reversed (ENC_DATA[5] at pin 19, ENC_DATA[0] at pin 30).
Connector Definition Owner:
Stack-Interposer/Board_Layout.md §1.
Straight/vertical 30-contact 2×15 2.54mm pitch connector on the top surface, Stack-Output side. The Stack-Output Board J6 (right-angle connector on the Stack-Output bottom edge) mates with J1 from above when the Stack-Output Board is assembled vertically alongside the Stack-Interposer.
- MPN: TMMH-115-01-L-D-ES (Samtec 30-position 2×15 straight/vertical male)
- Mouser PN: 200-TMMH11501LDES
- DigiKey PN: 612-TMMH-115-01-L-D-ES-ND
- JLCPCB PN: Global Sourcing
-
Signals carried (bidirectional):
- Stack-Output → Stack-Input: SIG-BLOCK-A ENC_DATA[5:0] (from Stack-Output J5), SIG-BLOCK-E TTD (from Stack-Output J3), and SIG-BLOCK-G ACTUATE_REQUEST forward (per DEC-093)
- Stack-Input → Stack-Output: SIG-BLOCK-D ENC_DATA[5:0] return (into Stack-Output J5 for ROT chain return traversal) and SIG-BLOCK-H ACTUATE_REQUEST return (per DEC-093)
- Mating connector on Stack-Output Board: Stack-Output J6 (SQT-115-01-L-D-RA right-angle female)
Pinout: see
Board_Layout.md §1.
Connector Definition Owner:
Stack-Interposer/Board_Layout.md §2.
Straight/vertical 30-contact 2×15 2.54mm pitch connector on the top surface, Stack-Input side. The Stack-Input Board J6 (right-angle connector on the Stack-Input bottom edge) mates with J2 from above when the Stack-Input Board is assembled vertically alongside the Stack-Interposer.
- MPN: TMMH-115-01-L-D-ES (Samtec 30-position 2×15 straight/vertical male)
- Mouser PN: 200-TMMH11501LDES
- DigiKey PN: 612-TMMH-115-01-L-D-ES-ND
- JLCPCB PN: Global Sourcing
-
Signals carried (bidirectional):
- Stack-Output → Stack-Input: SIG-BLOCK-A ENC_DATA[5:0], SIG-BLOCK-E TTD, and SIG-BLOCK-G ACTUATE_REQUEST forward (per DEC-093)
- Stack-Input → Stack-Output: SIG-BLOCK-D ENC_DATA[5:0] return and SIG-BLOCK-H ACTUATE_REQUEST return (per DEC-093)
- Mating connector on Stack-Input Board: Stack-Input J6 (SQT-115-01-L-D-RA right-angle female)
Pinout: see
Board_Layout.md §2.
-
Stackup: 4-layer per
design/Standards/Global_Routing_Spec.md §2.3.1.
| Layer | Function | Notes |
|---|---|---|
| L1 (top) | GND pour — shielding | Continuous copper pour; J1 and J2 land patterns on top surface; no signal traces |
| L2 | Signal routing | All J1-to-J2 pin-to-pin traces; because J1 and J2 face each other in mirrored orientation, the physical trace routes will need to cross as they run between the two connectors; GND fill where not routed |
| L3 | Signal routing | Additional routing capacity for traces that cannot be routed on L2 alone due to the crossing pattern; GND fill where not routed |
| L4 (bottom) | GND pour — shielding | Continuous copper pour; no signal traces |
- Manufacturer: JLCPCB. Single-sided assembly.
- Fillets: 2.0mm rounded PCB corners.
- Mounting Holes: MH1–MH4, M3 PTH (3.2mm drill), tied to GND_CHASSIS per GRS §4. No BOM entry.
-
Signal trace width: All J1-to-J2 signal traces on L2/L3 routed at CI width per
design/Standards/Global_Routing_Spec.md §2.3.1, targeting 50 Ω controlled impedance.
- Thermal: No active ICs. No thermal concerns.
-
ESD: No ESD protection devices required. The Stack-Interposer Board is internal to the
Rotor Mini-Stack assembly and is not accessible during live mini-stack insertion or rotor swap.
Per
design/Standards/Global_Routing_Spec.md §9.
-
Data Plate: Per GRS §6 on Layer L4. Revision block:
STAPELBRUCKE [Stack-Interposer] V1.0(printed on board asSTAPELBRÜCKE). - Connector Pin-1 Markers: J1 and J2 silkscreen pin-1 markers required per GRS §7.1.
| RefDes | Specification | MPN | Manufacturer | DigiKey PN | Mouser PN | JLCPCB PN | Alt Supplier + PN | Notes | Footprint Available | Footprint Downloaded | Qty |
|---|---|---|---|---|---|---|---|---|---|---|---|
| J1 | 30-position 2×15 straight/vertical male (Stack-Output side) | TMMH-115-01-L-D-ES | Samtec | 612-TMMH-115-01-L-D-ES-ND | 200-TMMH11501LDES | Global Sourcing | – | Stack-Output interposer link — mates with Stack-Output J6 (SQT-115-01-L-D-RA); per Board_Layout.md §3 | ✔ | ✔ | 1 |
| J2 | 30-position 2×15 straight/vertical male (Stack-Input side) | TMMH-115-01-L-D-ES | Samtec | 612-TMMH-115-01-L-D-ES-ND | 200-TMMH11501LDES | Global Sourcing | – | Stack-Input interposer link — mates with Stack-Input J6 (SQT-115-01-L-D-RA); per Board_Layout.md §3 | ✔ | ✔ | 1 |
-
Design Log
- DEC-001 3v3-enig-used-throughout-3v3-system-removed-from-btb-interconnect
- DEC-002 poe-option-a2-selected-coilcraft-poe600f-12ld
- DEC-003 poe-output-12v-or-ing-priority-logic-required
- DEC-004 supercap-charge-current-05a-under-poe
- DEC-005 tps25980-efuse-replaces-tps259474l
- DEC-006 stusb4500-negotiates-15v5a-75w
- DEC-007 dual-interleaved-lmq61460-q1-5v-buck-12a
- DEC-008 tps25750-emulates-5v5a-pd-profile-to-cm5
- DEC-009 legacy-controller-probe-access-pin-14-reassigned-to-sw-led-ctrl
- DEC-010 inc-14-deferred-legacy-probe-access-esd-protection-post-prototype
- DEC-011 all-power-rails-on-power-module-3v3-enig-serves-rotor-stack
- DEC-012 u4-tps25750-replaced-with-tps25751drefr-nrnd-resolution
- DEC-013 l3-emi-inductor-changed-to-bourns-srp1265a-100m
- DEC-014 controller-board-uses-erf8-female-on-both-btb-connectors-for-blind-mate-assembly
- DEC-015 link-beta-connector-reduced-from-80-pin-to-40-pin-erf8-020-erm8-020
- DEC-016 jtag-controlled-impedance-and-series-termination
- DEC-017 minimum-4-layer-stackup-for-all-non-controller-boards
- DEC-018 connector-pinout-ownership-model
- DEC-019 poe-transformer-topology-acf-option-a-selected
- DEC-020 gnd-chassis-rib-clearway-enig-bond
- DEC-021 supercapacitor-bank-upgrade-2x2-2s2p-2x3-2s3p
- DEC-022 jdb-ft232h-clock-source-dedicated-12mhz-smd-crystal-selected
- DEC-023 jdb-gnd-chassis-omitted-mounting-holes-tied-to-gnd
- DEC-024 jdb-is-complete-jtag-master-controller-jtag-lines-are-pass-through
- DEC-025 cm5-shutdown-mechanism-hardware-driven-ltc3350-software-support-deferred
- DEC-026 rotor-position-encoder-as5600-replaced-with-single-track-capacitive-encoder
- DEC-027 rotor-position-readback-via-jtag-virtual-jtag-user0-udr
- DEC-028 split-dual-board-rotor-architecture
- DEC-029 supercapacitor-hold-up-specification-25f-abracon-cells-2s4p-20-s-at-15w
- DEC-030 5v-main-backup-switchover-transient-fix-r14-r30-c35
- DEC-031 cm5-virtual-keyboard-key-injection-feature-architecture
- DEC-032 settings-board-panel-mount-configuration-controls-with-cm5-override
- DEC-033 dsi1-display-connector-provision-for-optional-lid-touchscreen
- DEC-034 switch-hardware-refresh-settings-board-toggle-discrete-rgb-led-ruggedized-pm-sw1
- DEC-035 hid-keyboard-and-lightboard-use-a-40-position-qwerty-derived-layout-for-the-64-character-code-space
- DEC-036 link-beta-former-monitor-pins-reallocated-as-grouped-power-rails
- DEC-037 link-beta-pin-map-regrouped-around-dedicated-jtag-and-i2c-guard-bands
- DEC-038 controller-centric-dock-architecture-replaces-legacy-link-alpha-link-beta-backplane
- DEC-039 enclosure-connected-boards-use-gnd-chassis-daughterboards-are-exempt
- DEC-040 diagnostics-banks-removed-from-active-design-specs-pending-coupon-review
- DEC-041 encoder-modules-use-epm570-with-digital-debounce-and-role-by-programming
- DEC-042 encoder-port-pin-8-carries-hid-local-enc-active-n
- DEC-043 shared-actuation-module-replaces-direct-controller-servo-gpio
- DEC-044 fdc2114-internal-oscillator-selected-clkin-gnd
- DEC-045 rotor-samtec-erm8erf8-connectors-require-esd-protection
- DEC-046 bypassdecoupling-capacitor-voltage-rating-50v-retained-on-all-non-pm-boards
- DEC-047 or-ing-mosfet-corrected-to-csd17578q5a
- DEC-048 esd-protection-extended-to-host-side-rotor-facing-btb-connectors
- DEC-049 rotor-internal-headers-renamed-to-j-convention-connector-count-updated-to-8-bom-unified
- DEC-050 encoder-blade-terminal-refdes-corrected-from-bt-to-j-convention
- DEC-051 settings-board-renamed-to-user-settings-module-board-code-sbd-usm
- DEC-052 variant-specific-fdc2114-refdes-use-ab-suffix-convention
- DEC-053 extension-port-connector-upgraded-from-bhr-20-vua-20-pin-to-2bhr-30-vua-30-pin
- DEC-054 signal-net-renamed-pwr-but-pwr-but-n-active-low-suffix-conformance
- DEC-055 f-108-system-wide-reference-designator-and-requirement-id-consecutive-renumbering
- DEC-056 relocate-investigation-documents-to-board-owned-folders
- DEC-057 daughterboard-mounting-hole-specification-and-standoff-bom-ownership
- DEC-058 jdb-connector-upgrade-hat-headers-to-df40c-20-btb
- DEC-059 erm8erf8-stacking-height-confirmed-rotor-stack-assembly-specification-created
- DEC-060 jtag-daughterboard-renamed-to-jtag-module-jdb-prefix-replaced-with-jm
- DEC-061 pass-7-review-corrections-ctlstarotencamgrsstatus-updates
- DEC-062 ctl-poe-t1-selection-tdk-b82806d0060a120-topology-acf-flyback-acf-forward
- DEC-063 ctl-poe-l1-selection-yageo-pa4343333nlt-acf-forward-output-inductor
- DEC-064 ctl-poe-c17-final-part-selection-kemet-c0805c223k2racauto-22nf-200v-x7r-0805
- DEC-065 system-wide-stackup-code-correction-and-jlcpcb-authoritative-impedance-values
- DEC-066 grs-canonical-pcb-stackup-authority-consolidation
- DEC-067 am-sw1sw2-tactile-switch-rating-accepted-for-production
- DEC-068 pm-per-input-bulk-capacitors-and-output-source-quality-bulk-banks
- DEC-069 pm-per-input-polyfuse-protection-and-uvlo-resistor-recalculation
- DEC-070 mcp23017-i²c-silicon-restriction-gpb7gpa7-review-and-cfg-apply-n-reassignment
- DEC-071 usm-spdt-switch-dual-terminated-wiring-and-pull-down-resistor-removal
- DEC-072 review-pass-9-findings-and-resolutions
- DEC-073 ltc3350-rt-resistor-correction-332-kω-133-kω-amends-dec-030
- DEC-074 rename-cpld-reset-signal-sys-reset-n-cpld-reset-n
- DEC-075 tps25751-option-c-external-eeprom-isolated-i2ct-debug-header-on-power-module
- DEC-076 pm-3v3-architecture-redesign-3v3-main3v3-enig-rail-split-j4-dual-purpose-programming-j6-removal-and-q12-parallel-p-fet-selection
- DEC-077 retrospective-rotor-ttd-daisy-chain-no-series-termination-resistors-amends-dec-016
- DEC-078 cpld-reset-n-stator-buffer-bss138-n-channel-mosfet-new-decision-references-dec-077
- DEC-079 c20-voltage-rating-correction-25v-35v-amends-dec-072-bom-item-1
- DEC-080 retrospective-pm-and-stator-dock-connector-redesignation-amends-dec-038
- DEC-081 retrospective-rotor-ttd-no-series-resistor-policy-in-addition-to-dec-016
- DEC-082 10µf-bulk-reservoir-capacitor-upgrade-25v-0805-50v-1206-all-boards
- DEC-083 retire-all-boards-bomjson-consolidate-bom-authority-in-design-spec-files-and-consolidated-bom
- DEC-084 cypher-stack-architecture-migration-and-board-role-consolidation
- DEC-085 stack-output-j4-power-pin-zero-ohm-links-prototype-test
- DEC-086 cypher-input-common-variant-restructure-10-numeric-variant-single-i2c-address
- DEC-087 cypher-input-led-colour-architecture-moved-off-plain-bits-onto-local-rgb-select-circuit
- DEC-088 plugboard-jacks-wired-directly-to-cypher-board-spade-bank-j4j6-reserves-5v-main
- DEC-089 board-role-id-widened-to-4-bit-capability-bitmask-cpld-pin-freeing-and-j5-migration
- DEC-090 cypher-board-j3-stack-input-side-full-50-pin-allocation-and-actuate-request-in-out-n-signal-pair
- DEC-091 j3-esd-protection-extended-to-actuate-request-pins-and-actuation-gating-resolved-to-cypher-cpld
- DEC-092 cypher-board-j4-stack-output-side-full-50-pin-allocation
- DEC-093 actuate-request-end-to-end-signal-path-j4-rename-rotor-interposer-connectors-extended
- DEC-094 connector-ownership-reassignment-for-reused-chain-templates
- DEC-095 actuate-request-esd-protection-completed-stack-output-passive-wiring-defined
- DEC-096 stack-blanking-board-corrected-actuate-request-bridging-added
- DEC-097 cypher-j3-actuate-request-out-n-wired-as-round-trip-verification-input
- DEC-098 controller-cypher-dock-split-power-molex-signal-samtec-amends-dec-038-dec-080
- DEC-099 cm5-i2c-bank-architecture-mipi0-to-mipi1-swap-pwm-gpclk-reservation
- DEC-100 jtag-module-actuation-module-retirement-from-controller-board
- DEC-101 cypher-ina219-i2c-address-aligned-to-pm-default
- DEC-102 cypher-ft232h-3v3-vregin-self-powered-5v-usb-net-retired
- DEC-103 hid-usm-hub-connector-topology-rework
- DEC-104 user-settings-module-role-reworked-as-hid-colour-audio-hub-and-jtag-i2c-spine
- DEC-105 cfg-route-moved-to-full-cm5-software-control-physical-usm-switches-retired
- DEC-106 cypher-plugboard-reduced-to-mechanical-connector-only-board
- DEC-107 usm-hid-connector-four-colour-style-signal-expansion
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