Laboratorios, prácticos y teóricos de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
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Updated
Jul 24, 2024 - SystemVerilog
Laboratorios, prácticos y teóricos de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
Laboratorio 1 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
Mano Machine implementation in SystemVerilog
GameBoy Audio Processing Unit
Developing RISC-V CPU
Impletations of Computer Architecture components and RISC-V CPU (SystemVerilog)
A 5-stage pipelined 64-bit ARM processor; implemented in SystemVerilog
A pipelined (partial) implementation of the RV32I specification
A repository consisting of all the project files and codes for RISC-V Processor design using Transaction Level Verilog.
Minimalistic RV32I RISC-V Processor in System Verilog
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
🖥️ Digital Design and Computer Architecture
Single-cycle single-core MIPS processor
Designing simple 5-stage pipelined RISC-V processor (Lab assignment of "Computer Architecture" class)
5 stages RISC pipelined processor with multiple instructions implemented in verilog including ALU Operations, Interrupts as a state machine, Jumps and branching instructions, Memory operations and more.. following Harvard architecture.
MIPS multi cycle Verilog Implementation
MIPS Single cycle Verilog Implementation
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