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control-logic

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mirseo / JSilicon

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JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.

asic rtl verilog finite-state-machine uart alu hdl verilog-hdl open-source-hardware serial-communication rtl-design digital-designs 8bit-cpu chip-design tinytapeout control-logic prototype-core embedded-core minimal-cpu-core
  • Updated Oct 19, 2025
  • SystemVerilog

Awais-Asghar / 5-Stage-Pipelined-RISC-V-Processor-on-FPGA

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A 5-Stage Pipelined RISC-V Processor designed and implemented on FPGA (Artix-7 Nexys A7). Supports RV32I instructions set (R, I, S, B, U, J types) with ALU, control unit, hazard detection, forwarding, and pipeline registers. Verified through simulation and hardware testing with optimized timing and 4× performance gain.

fpga processor systemverilog pipelining computer-architecture hazard-detection risc-v system-design riscv32 datapath-design pipelined-processor control-logic
  • Updated Oct 13, 2025
  • SystemVerilog

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