Reimagining CPU Architecture from the Outside: Pursuing the 5M-strat through unconventional logic design.

An open-source design for an 8-bit RISC CPU

A microarchitecture simulation toolkit for analyzing modern branch prediction logic, including GShare and Perceptron. Implements cycle-accurate behavior for rigorous sensitivity analysis across ML, I/O, and general-purpose workloads. Designed to optimize processor pipeline efficiency through advanced algorithmic modeling.

Custom 16-bit CPU implemented in Logisim with a Python assembler that encodes assembly-style instructions into machine-formatted memory images for execution and simulation. Includes CPU datapath, control signaling, ALU operations, and load/store behavior.