fpu
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Fully synthesizable and paramterizable, IEEE-754 compliant Floating Point Unit (FPU) in systemverilog. Supports fused multiply add, division and square root operations.
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Aug 5, 2024 - SystemVerilog
A simple Floating-Point arithmetic unit - implemented in SystemVerilog
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Mar 11, 2024 - SystemVerilog
Computer Architecture - Informatyka PG 2022/2023 - labs & notes
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Feb 17, 2024 - Assembly
This repository contains an assembly program written in AT&T syntax called FPU-Analyzer. The program analyzes a series of floating-point numbers and calculates their sum and average.
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Aug 6, 2023 - Assembly
Double Extended precision FPU calculator (80 bits)
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Mar 26, 2023 - Pascal
Simulation model of a mathematical processor (Floating point unit, FPU)
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Nov 30, 2022 - Python
Specialized FPU for Fast Inverse Square Root Algorithm
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Nov 10, 2022 - Verilog
X86-64 bilateral instruction tokenizer implemented in C. Supports the following processor extensions: AES, AVX, AVX2, AVX512, FMA, MMX, SSE, SSE2, SSE3, SSE4, x87(FPU), VMX. In order to ease testing, a diassembler which transforms tokens into compilable assembly (for NASM compiler) has been implemented.
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Oct 2, 2022 - C
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