VHDL Implementation of Modulo2 Line by Matrix Multiplication (with Tutorial Series on Steemit)
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Updated
Oct 19, 2020 - VHDL
VHDL Implementation of Modulo2 Line by Matrix Multiplication (with Tutorial Series on Steemit)
Assignment 6, Digital Logic Design Lab, Spring 2021, IIT Bombay
Flappy Bird VHDL
A team-project about a fem vending-machine I had in 2nd year of uni
4-bit calculator with all operations we set up for calculator. It have some main parts which are FSM(Finite State Machine) which has MOP(Micro-operations). Datapath that includes calculator's brain which is ALU(Arithmetic Logic Unit), multiplexers and hexadecimal decoder.
Design in VHDL of an hardware component for the Logic Circuit Design course @ PoliMi
Signed / unsigned multiplier / divider used by a microcode-driven prime number generator
Finite-State Machine Design of a Simple Car Security Alarm on FPGA
Simple calculator implemented in VHDL using FSM logic
Integrated and programmed a VGA Interface using the Altera DE1 to output in synchronization with a custom programmed finite-state machine.
Computer Architecture Project using VHDL
FSM and Cache design for practicing the concepts of computer architecture
Prova Finale di Reti Logiche - Polimi Ingegneria Informatica - A.A. 2019-2020
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