Test suite designed to check compliance with the SystemVerilog standard.
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Updated
Jul 8, 2024 - SystemVerilog
Test suite designed to check compliance with the SystemVerilog standard.
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
UVM and Systemverilog based test benches for functional verification of a RAM module
An open source, parameterized SystemVerilog digital hardware IP library
100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore
Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster
Examples with UVM
YM2149 / AY-3-8910 Programmable Sound Generator in SystemVerilog and Verilog. Offers dual PSGs, programmable stereo mixer with bass and treble controls, standard I2S 44.1KHz or 48KHz 16-bit digital audio out, and built-in floating point system clock divider/generator.
Synthesizable SystemVerilog IP-Core of the I2S Receiver
Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
A systemverilog implementation of the data structures: priority queue, queue and stack
Desarrollo de un circuito decodificador de Gray por medio del HDL SystemVerilog
SystemVerilog Logger
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