HDL support for VS Code
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Updated
May 21, 2024 - TypeScript
HDL support for VS Code
An abstraction library for interfacing EDA tools
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Practice Codes of Verilog Language
Developing different projects in order to understand how the Icarus Verilog tools work with GTKWave and Yosys.
SystemVerilog files for simulating a complete Game Boy system with DMG-CPU B chip
A generic verification interface to Icarus Verilog using TCP sockets
📦 Prebuilt Icarus Verilog simulator package for x64 Linux.
All basic to advanced hardware models which are used in VLSI Frontend Design using Verilog HDL
RTL implementation of a MoldUPD64 receiver.
Guides on how to install a SystemVerilog toolchain on different operating systems
This Repository contains my code for the Digital System Design (DSD) lab during my 3rd Semester of B.Tech.
A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
Some basic hardware and logic designs and their respective testbenches written in Verilog HDL
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