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microarchitecture

Here are 5 public repositories matching this topic...

Dmitriy0111 / nanoFOX

A small RISC-V core (SystemVerilog)

education programming cpu systemverilog risc-v microarchitecture

Updated Aug 26, 2019
SystemVerilog

yuri-panchul / tt08-adder-with-flow-control

Submission for Tiny Tapeout 8 - Verilog HDL Projects. An adder with a separate flow control for each argument and the result.

verilog systemverilog verilog-hdl microarchitecture systemverilog-hdl verilog-project verilog-code

Updated Sep 5, 2024
SystemVerilog

dominiksalvet / super-riscv

Superscalar dual-issue RISC-V processor

open-source pipeline core rtl forwarding systemverilog gtkwave testbench superscalar in-order risc-v microarchitecture low-power verilator ahb3-lite instruction-level-parallelism dual-issue riscv-gcc

Updated Jul 31, 2024
SystemVerilog

AliLRS / RISC-V_Microprogrammed

riscv computer-architecture risc-v microarchitecture microprogrammed microprogrammed-control-unit

Updated Aug 5, 2023
SystemVerilog

naftali10 / Single-Cycle-MIPS

A System Verilog processor design of a single cycle MIPS architecture

mips architecture mips-architecture microarchitecture verilog-processor

Updated Jan 8, 2021
SystemVerilog

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