An abstraction library for interfacing EDA tools
-
Updated
Jul 8, 2024 - Python
An abstraction library for interfacing EDA tools
Repurposing existing HDL tools to help writing better code
🪀 Tool to play with HDL (inspired by EdaPlayground)
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
A Python-based IP Core Management Infrastructure.
Example of Python and PyTest powered workflow for a HDL simulation
An assembler that transfers your assembly code into .mem files for simulation in modelsim. Instruction set, opcodes assignment, and sample files included.
⚡👌 ModelSim vcom/vlog plugin for SublimeLinter. Linting for VHDL and Verilog/SystemVerilog.
SublimeLinter plugin for linting Verilog and SystemVerilog with Modelsim vlog
SublimeLinter plugin for linting VHDL with Modelsim vcom
Add a description, image, and links to the modelsim topic page so that developers can more easily learn about it.
To associate your repository with the modelsim topic, visit your repo's landing page and select "manage topics."