Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
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Sep 15, 2023 - Verilog
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
Install Intel FPGA 'Quartus Prime' software on remote servers
SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
Tutorial de instalação do Quartus Prime no Linux
A recreation of Williams Defender 1981 arcade game for DE10-Lite FPGA dev board, written in VHDL.
A Python-based IP Core Management Infrastructure.
Remote control infrared signal receiver programmed in VHDL for a Terasic DE1-SoC board.
Full tutorial about how to install Quartus Prime software in different systems
Sends data from an ADC to a UART-USB interface
Script to build the bootloader (u-boot) and bring all components to a bootable image for Intel (ALTERA) SoC-FPGAs
This is a Quartus Prime FPGA project testing the functionality of the LogiFind Altera Cyclone IV EP4CE6E22C8N Development Board. This product can also be found on eBay where I bought it from. I hope to provide base code that will help others in their learning with this development board.
An 8-bit RISC based processor designed in verilog with x86 instructions.
Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller
Implementation of a mips-based processor architecture using SystemVerilog and VHDL
This project is an implementation of a special-purpose processor that can calculate greatest common multiple (GCM) and least common factor (LCM) for two inputs based on input operation code (Opcode)
AES implementation using verilog
Game development library for MKR VIDOR 4000
Design MMU for socfpga-linux 4.11. Test with Altera DE2-115.
FPGA SOC Mario NES in SystemVerilog. Built on a DE-10 Lite FPGA, synthesized in Quartus Prime 18.1
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