RISC-V
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 49 public repositories matching this topic...
Syntacore scr1 iALU verification example
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Mar 7, 2024 - SystemVerilog
An attempt at making a customised RISC processor with five pipelined stages and supporting all RISC-V instruction set
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May 13, 2023 - SystemVerilog
Fully implemented 3 staged pipelined RISC-V processor with hazard detection unit. Hazard detection unit solves the hazards by stalling and forwarding technique. CSR and MRET Instructions are also supported as they can configure and manage all the interrupt/exceptions.
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Jan 9, 2023 - SystemVerilog
Creating a risc-v processor
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Apr 4, 2024 - SystemVerilog
Implementation of 3 stage pipelined processor based on RISC-V Instruction Set Architecture
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Dec 30, 2023 - SystemVerilog
SV/UVM based instruction generator for RISC-V processor verification
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Nov 4, 2019 - SystemVerilog
Experimental RISCV implementation
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Apr 19, 2021 - SystemVerilog
RISC-V SoC
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Sep 4, 2023 - SystemVerilog
A Pipelined Implementation of the RV32I Processor
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Jan 12, 2024 - SystemVerilog
Complete simulation environment for SiFive freedom RISCV CPU platforms
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Jan 2, 2021 - SystemVerilog
A pipelined, in-order implementation of the RV32I ISA
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Aug 9, 2020 - SystemVerilog
Undergraduate level RISC-V microcontroller
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Oct 12, 2022 - SystemVerilog
Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF
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May 9, 2022 - SystemVerilog