#
rtl
Here are 26 public repositories matching this topic...
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
boom
rocket
rocket-chip
chip-generator
chisel
riscv
rtl
peripherals
soc
out-of-order
superscalar
risc-v
firesim
accelerators
chipyard
hwacha
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May 23, 2024 - Scala
SonicBOOM: The Berkeley Out-of-Order Machine
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Updated
May 17, 2024 - Scala
[HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
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Updated
May 3, 2024 - Scala
A Chisel RTL generator for network-on-chip interconnects
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Feb 27, 2024 - Scala
A 32-bit CPU being developed in SpinalHDL
cpu
fpga
gcc
rtl
binutils
hdl
32-bit
spinalhdl
gcc-backend
binutils-backend
gcc-port
binutils-port
flare32
flare32-cpu
spinal-hdl
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Updated
Jan 6, 2024 - Scala
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