Single Cycle CPU design (RISC architecture) developed in Xilinx ISE 14.7 using Verilog
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Updated
Nov 7, 2018 - Verilog
Single Cycle CPU design (RISC architecture) developed in Xilinx ISE 14.7 using Verilog
A Verilog implementation of a single cycle processor using the LEGv8 instruction set architecture
A RISC-V Single Cycle Processor which is done in verilog.
This repository is created to build a single cycle processor and converting it to a 5-stage pipelined processor capable of executing a bubble sort program.
A simplified MIPS machine simulator using SystemVerilog, developed with three different micro-architectures: single-cycle, multi-cycle and pipelined.
LEGv8 CPU implementation and some tools like a LEGv8 assembler
Single and Multi-cycle ARM processors implemented using VHDL
Mips Single-Cycle, Computer Architecture course, University of Tehran
A 32-bit CPU which includes an ALU, a Register File, Control Unit, Data and Instruction memory
Spring 2021 UCM CSE140 (Single-cycle MIPS CPU) & (Pipelined MIPS CPU)
MIPS Single-Cycle Microarchitecture Processor
A single cycle pipeline processor based on MIPS instruction set architecture (ISA)
👷♀️Computer Architecture Course Projects, University of Tehran
A 32-bit microprocessor with 42 instructions (including multiplication and division) and 8 X 32 registers and 2048 X 32 Ram with shared stack. An assembler is also available to write programs on the microprocessor using 8086-like assembly.
Single Cycle Processor with an ISA like MIPS x32 implemented in VHDL.
Supports 12 MIPS instructions
RISC-V 32IM - Dobby SOC
This is a simple implementation of the MIPS single cycle processor that is described and taught in the book of "Computer Organisation and Design" from Patterson and Hennessy.
This project was designed to run on Nexys A7 Artix-7 FPGA Trainer Board. This processor written in System Verilog can run I-Type, R-Type, B-Type, S-Type RISC-V commands. The current instruction set that has been uploaded here finds the greatest common divisor of two numbers.
This repository contains files related to Computer Architecture Lab (Autumn 2022).
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