synthesis
Here are 32 public repositories matching this topic...
Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.
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Jun 9, 2021 - Verilog
Verilog description of an ALU along with the Cadence Genus tcl script files needed to synthesize it.
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Jul 17, 2020 - Verilog
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Nov 30, 2023 - Verilog
SerDes RTL design, verification using UVM and Physical design.
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May 26, 2024 - Verilog
5-Day TCL begginer to advanced workshop by VSD
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Jan 24, 2024 - Verilog
🎓💻University of Tehran Digital Logic Design Lab Course Projects - Spring 2021
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Nov 20, 2021 - Verilog
Modified Non-Restoring Square Root in verilog
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Aug 10, 2020 - Verilog
This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.
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Mar 8, 2024 - Verilog
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
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May 21, 2024 - Verilog
RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.
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Dec 11, 2020 - Verilog
designed to control the doors, windows, fire alarm and the temperature. Each process being automated is associated with a sensor.
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Jan 11, 2022 - Verilog
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be …
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Dec 3, 2023 - Verilog
PrUcess is a low-power multi-clock configurable digital processing system that executes commands (unsigned arithmetic operations, logical operations, register file read & write operations) which are received from an external source through UART receiver module and it transmits the commands' results through the UART transmitter module.
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Apr 29, 2023 - Verilog
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